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In this week's Whiteboard Wednesdays video, Bob Salem explains WiGig (IEEE 802.11ad), the next-generation wireless communication interface. Bob details how applications including entertainment, small office, small corporate groups, and hotspots all benefit from this powerful, wireless interface.

https://youtu.be/eT1sT4Y_FjQ

With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de-highlight all nets associated with a component is offered in all applications modes. Hover over a symbol(s), then use the RMB to access the ‘Highlight Associated Nets’ command. Nets assigned the DC Voltage property are ignored.

Here are the steps to accomplish highlighting nets:

1. Using any one of the application modes, hover…

Link training is the first stepping stone to enabling the communication channel between source and sink devices. This is where the electrical characteristics of the link along with the bitrate are fixed, and are subsequently used for the data transfers...

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM. The agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. I sat down with Martin Lund, Senior Vice President of Cadence’s IP Group, to talk about the deal.

Q: What’s…

In this week's Whiteboard Wednesdays video, Chris Rowen talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices, applications, and services. And the Cadence Tensilica team, which has been attending this event for a decade, generally has something up its sleeves when the booth opens for business each year.

This time was no exception. The company announced that DTS’s Headphone:X immersive sound technology has been optimized for the Cadence…

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the latest enhancements of PCI Express (PCIe) Gen 4 and how these enhancements address the goals of increased bandwidth while maintaining software compatibility and keeping power consumption and implementation costs down.

http://youtu.be/Keh-utK5YKo

Just as IP components offload design effort, verification IP (VIP) components offload verification effort. VIP components are used to monitor traffic and substitute for selected master and slave components to enable controlled stimulus generation and coverage collection within an SoC design. To be effective in verifying CHI-based designs, the VIP must deliver three major capabilities. They are:

1. Stimulus generation…

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic system design. Steve Roddy should know. He’s had a ringside seat to those changes—and Mobile World Congress—for years.

Roddy, senior group director for Tensilica marketing, said during MWC 2015 that system design is a much different challenge than it was a decade ago. (Tensilica, which Cadence acquired in 2013, has…

1. Voltus-Fi Power Analysis Support and Power Grid View Generation—Voltus-Fi to Voltus Flow

The Voltus-Fi to Voltus flow provides the complete Cadence power integrity solution for full-chip power integrity analysis for all designs, featuring accurate transistor EMIR analysis and high-quality analog IP grid modeling. This application note covers the process of Voltus-Fi flow based on the 28nm…

What is WiGig

WiGig is the name given to a high-speed multi-gigabit wireless communications standard over unlicensed 60GHz radio frequency band established by the Wireless Gigabit Alliance in 2007. Since then it has become part of the WiFi Alliances and established as one of the IEEE 802.11ad protocol. As part of the WiFi Alliances, WiGig tri-band-enabled devices will operate in the 2.4, 5 and 60GHz radio band.

WiGig…

In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy equation for processors and how a configurable processor architecture provides the flexibility to optimize power for a given application. 

http://youtu.be/gMrUIqovAIU

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached End of Support as of 12/31/2014.

1.  Where do I find the support lifecycle dates (e.g., End of Support) for Cadence releases?

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000051SLEAY&pageName=ArticleContent

2.  Where do I find the product lifecycle letters?

https://support.cadence.com/apex/ArticleAttachmentPortal…

The 16.6 Allegro PCB Editor release ‘Find by Name’ list now supports hierarchical database objects - Diff Pair, Match Group, Region, for example:

16.5 Find by Name:

16.6 Find by Name:

Read on for more details …

Invoke the ‘Assign Color’ command.

Select ‘Diff Pair’ from the ‘Find by Name’ list.

Click the ‘More’ button.

Select a few Diff Pairs from…

After reading the rest of this blog, you might guess the truth, which is that my "designing" skills go back to the 8086 processor! In this blog, I have used a 64-bit register (Well, I could make it 16-bit, but…)  in the example, just to show that this issue is still relevant today.

At any rate, the e verification issue that I describe here seems to be a common issue for many users.

Assume that, in the…

In this week's Whiteboard Wednesdays video, Herbert Rivera-Sanchez discusses the Cadence Verification IP (VIP) Ease of Use Project. This project addresses three main areas of concern: works out of the box, provides consistent integration and provides basic training to quickly bring customers to a productive level in a short time.

http://youtu.be/fbsyfdPq4ho

A customer working on a VIP component identified that the performance of one of their protocol checkers, written in ‘e’, is significantly worse than the performance of the competing solutions. Profiler reports of a representative test case pointed to a few complex methods, which consumed about 90% of the time. What stood out in these methods was the use of the pop0() pseudo-method on a couple of list buffers. This…

Hello my fellow Digital Designers,

I'm sorry I haven't been around the blogs much lately. We've had a lot of exciting design work going on that has kept me pretty busy. I hope all of you are having a great 2015 so far. Just a heads up - all links below require a Cadence Online Support account.

Our Educational Services team has been busy putting together some short videos called Training Bytes. These are…

This year’s Mobile World Congress (MWC) in Barcelona, March 2-5, should be the largest, most exciting MWC ever. I’ve been going since 2006, and I’ve seen the show outgrow the old convention area and now, with over 1900 exhibitors, outgrow the new Fira Gran Via. We’re lucky that the Tensilica group has been going for a long time, as getting a space to exhibit now is almost impossible.

Our booth…

In this week's Whiteboard Wednesdays, Avi Behar follows up on his earlier video on the ARM® AMBA® protocol family. Watch this video for a deep dive on each of the protocols in the ARM AMBA family to learn how they are commonly used.

http://youtu.be/LQ5UVwEwZv4

CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the Santa Clara Convention Center. For the first time, we’ll have a very interesting 2-day IP track at the conference. Sign up now!

Check out our exciting agenda in Track 7. Some of the highlights include:

• External Memory Architectural Choices for Terabit-Class Devices by Broadcom
• Applying Maslow’s Hierarchy of Needs to IP Reuse…

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface) specification that enables processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in enterprise markets, such as servers and networking. Coherent architectures have existed for many generations of CPU designs, but verifying adherence to coherency rules has always been…