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I wrote earlier that the sheer vastness and potential for IoT designs require a different way of thinking about system implementation. There just isn't a single controller architecture that meets all IoT requirements, such as multiple sensors, an innovative user experience, wireless protocol support, and various security requirements.

And if a single controller architecture is not the answer, do we just lean on other…

The Tensilica® group at Cadence has just published a 37-page application note on a Wi-Fi 802.11ac transceiver used for WLAN (wireless local area network), and it's full of really useful information.

This transceiver design is architected on a programmable platform consisting of Tensilica DSPs, using an anchor DSP from the ConnX BBE family of cores in combination with a smaller specialized DSP and dedicated hardware…

The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to the Design Rule Checks (DRC) system. The Custom DRC provides the ability to extend the Capture DRC system to user-defined rules.

Open an Allegro Design Entry CIS design database (.dsn) file, select a design in Project Manager, and click menu Tools > Design Rules Check:


Click on Configure Custom DRC:


The following DRCs are provided as examples…

A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:

• During manufacturing they are used to verify that a newly assembled device is working correctly. Any equipment that fails this testing is either discarded or sent for rework.
• After sale of the device to a customer, test points may be used at a…

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design.

Suppose you have two verification components, each driving its own portion of the DUT (for example, two protocols driving a DUT, one implemented in e and the other in System Verilog).

In this case, you would have two separate sequence-driven, end-of-test mechanisms - one for each framework.

An issue arises when one of the frameworks drops its last TEST_DONE objection. In this case, that framework will begin simulation…

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.

Application Notes

1. Cadence Online Support Release Highlights

New features for searching and filtering, viewing cases and providing feedback

2. Generic Process Design Kit Downloads 

Get the latest versions of the Cadence Generic Process Design Kits (GPDK) and standard cell reference libraries, which are provided…

You know we live in astonishing times when you can start your car by talking into your phone. But the era of the Internet of Everything--for all the great technology it has begun to enable--is filled with challenges for electronics design engineers.

Consider:

• Bill of materials, especially for tiny and ubiquitous IoT nodes, need to shrink if the market is going to expand. Five-dollar BOMs will not unlock big market…

Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the bumps is perfect. But, what about for wire bond designs?

Fingers and power/ground rings need to be exposed so they can be bonded to, but visibility of surrounding metal should be minimized. At the same time, it is…

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration:
Logical design integrator
  Responsible for front-end design
Physical design integrator
  Responsible for back-end design

A logical design integrator or physical design integrator needs to enable Team Design and assign and inform team members to work on the design project from the list of designers…

As the 3-D memory market matures,  it continues to incubate new application opportunities and confront new challenges.

Some of the challenges faced by 3D memory adoption range from technology to cost and design. 

On the technology front, many of the initial challenges around the interconnect reliability and scalability of through-silicon vias (TSV), interposer development and chemical mechanical polishing (CMP) have been…

The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied to parallel memory interfaces, such as DDR4. And it all makes sense.

Back when PCI Express initially came out at 2.5Gbps, we saw a seismic shift in how simulation and…

The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance bottlenecks found in SystemVerilog, UVM, and general verification environments, profiling requirements have changed for the design and verification environment. The…

Each era of electronics innovation is generally marked by a dominant end application: Mil/Aero (1960-70s), Computing/PCs (1980s), Communications (1990s), Internet/Mobile (2000s). And each-for the most part-had a signature interface.

These technology eras were usually dominated by two interfaces: a keyboard (computing) or a keypad (communications). But that changed with the introduction of the smartphone and touchscreen…

Just a brief post this week to mention a new capability for Allegro Design Entry HDL (DEHDL) that was made available in the 16.6-QIR4 release.

You can now employ net renaming without loss of data:

• All instances of the net will be renamed to a new name
• All properties and constraints captured on the net instances retained
• All membership to net objects are retained

The net rename capability is available as:

• A menu…

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need for advanced error correction. Lou also details the Berlekamp Chaudhuri Hocquenghem (BCH) algorithm. Learn how this algorithm is implemented and how engineers are using it in their designs today.

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more thoroughly, and with less effort. While innovating and providing great products and technologies, the VIP team at Cadence also believes that it is important to keep creating self-help knowledge resources. These resources provide an easy way for you to learn about and stay productive with these products, technologies, and methodologies…