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SoC and IP: M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG

Jacek Duda

If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across…
- 9 Jul 2013
System, PCB, & Package Design : What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!

Jerry GenPart
The 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in the area of schematic generation.

Some of the highlights:
Rules file can be added via the Component Browser as Real Interfaces
FPGAs can be linked to corporate symbols/footprints
Virtual Interfaces can be converted to Real Interfaces
FSP generated symbols can be customized as split symbols
Pin directions for generated symbols can be customiz…
- 9 Jul 2013
Verification: How-To AppNotes on Cadence Palladium-XP Help Users Get the Basics Right

SumeetAggarwal

In simulation acceleration, there are multiple reasons for using gate-level netlists in place of RTL code. One reason is the reuse of mature code or third party IP that is supplied in netlist format because it is no longer the focus for verification,...
- 8 Jul 2013
System, PCB, & Package Design : What's Good About Capture’s Find Command? 16.6 has a few new enhancements!

Jerry GenPart
The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements to the Find command.

You can now:
Search for a property with a specific value
Use regular expressions for matching values
Use global find and replace for offpage connectors

Read on for more details…

In earlier versions of Allegro Design Entry CIS (Capture/Capture-CIS) you could only search for strings and if they matched in property…
- 8 Jul 2013
Verification: The Art of Modeling in e

teamspecman

Verification is the art of modeling complex relationships and behaviors. Effective model creation requires that the verification engineer be driven by a curiosity to explore a design's functionality, anticipate how it ought to work, and understand what should be considered an error. The model must be focused and expressed as clearly as possible, as it transitions from a natural language to a machine-understandable…
- 30 Jun 2013
Analog/Custom Design: OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for Smart Devices

Sathish Bala

I had the great opportunity to represent Cadence at the Design Automation Conference (DAC) at Austin a few weeks back. In my role as a Mixed-Signal Solutions evangelist at Cadence, I was thoroughly amazed by the excitement from the ever growing design community at this year's DAC. For Cadence, this was an excellent opportunity to showcase the various technologies covering system, IP and SoC designs.

A common theme…
- 28 Jun 2013
Verification: Rapid Adoption Kit (RAK) -- Creating UVM Verification Environments with Hardware-Assisted Verification

SumeetAggarwal

The hands-on, learning-by-doing, trying, discovering, failing and learning approach is not unique. John Dewey initially promoted the idea of "learning by doing." Teams within Cadence took this idea and uniquely developed a new content type,...
- 28 Jun 2013
SoC and IP: Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences

Arif Khan

One of the hottest (or should I say coolest – because low power is so important) new standards is PCI Express® (PCIe) over M-PHY, or M-PCIe. To implement it properly, it’s essential that the controller and PHY work well together as the interface specification between them is, to put it mildly, loosely defined.

We just finished the PCI-SIG 2013 conference at the Santa Clara Convention Center, and our M…
- 27 Jun 2013
Verification: Forte and Cadence at DAC: How to Deploy High-Level Synthesis

Jack Erickson

It's no secret that the transition to high-level synthesis (HLS) has historically gone more slowly than expected. There were a number of reasons for this - the early tools could not successfully synthesize control logic, they could not match the ...
- 26 Jun 2013
System, PCB, & Package Design : What's Good About DEHDL’s Hierarchical Split Symbols? The Secret's in the 16.6 Release!

Jerry GenPart

The complexity of the designs is constantly increasing and more and more logic is being placed inside hierarchical blocks. This leads to an increase in the number of interfaces that are exposed by the hierarchical block. The increased number of interfaces means more pins are required on the block symbol. In many cases, the block symbols become so big (e.g. FPGAs, large pin count devices) that they cannot be placed on a
…
- 25 Jun 2013
System, PCB, & Package Design : Catch, Correct, and Prevent Common Package Design Errors with the 16.6 Cadence APD/SiP Integrity Check Tools

Jeff Gallagher

Designing an IC package substrate is a complex task. From picking the right materials and substrate cross-section to configuring your design rule constraints and identifying your voltage nets, it can be easy to make a mistake no matter how careful yo...
- 24 Jun 2013
SoC and IP: MIPI Alliance Meeting Reflects the Rapid Growth of the Mobile Market

Jacek Duda

Let me start this entry on a bit of a personal note. As a Pole, I was very happy to learn some time ago that the 2013 European meeting of the MIPI Alliance would take place in my home country. Later, it turned out that Cadence was to acquire the IP business of Evatronix, the company I worked at. These events ended up taking place one right after another—on Thursday, June 13, Cadence completed its acquisition of…
- 24 Jun 2013
System, PCB, & Package Design : Simultaneous Switching Noise Analysis – The Earlier the Better

TeamAllegro

The evolution of signal integrity analysis is similar to many electronic design tasks. First, best practices were followed. Second, analysis tools were used to verify final designs. Then, to reduce design re-spins, what-if analysis techniques were created to drive constraints that could then be verified at the end of the design cycle.

Because of tight schedules and time to market pressure, there is often little time…
- 23 Jun 2013
Analog/Custom Design: SKILL for the Skilled: The Partial Predicate Problem

Team SKILL

The partial predicate problem describes the type of problem encountered when a function needs to usually return a computed value, but also may need to return a special value indicating that the computation failed. Specifically, the problem arises if the caller cannot distinguish this special value from a successfully calculated value. In this posting of SKILL for the Skilled, we look at several ways to attach this problem…
- 19 Jun 2013
Verification: Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification

Jack Erickson

I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. ...
- 18 Jun 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Net Groups? See for Yourself in 16.6!

Jerry GenPart

Just a brief blog today about a new feature in Allegro PCB Editor.
A new net grouping mechanism has been added in Allegro PCB Editor 16.6 called ‘NET_GROUPS’. Essentially, the Net Group replaces the bus object.
A Net Group is a collection of net objects. Different types of net objects, such as nets, buses, differential pairs, and XNets can be added as members of a Net Group. A net object can be a member of…
- 17 Jun 2013
Analog/Custom Design: Virtuosity: 10 Things I Learned in May by Browsing Cadence Online Support

stacyw

May was a big month for new videos. It was also a month that saw the release of Virtuoso IC6.1.6, with lots of great new features and the rollout of new enhancements to the Cadence Online Support website.
Videos
1. DMS Basics Series
This is a great series of 10 videos covering various topics in mixed-signal verification, real number modeling, and mixed-signal connectivity. You'll also notice all 10 videos referenced together…
- 14 Jun 2013
System, PCB, & Package Design : What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements!

Jerry GenPart

The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support the generic via exchange.
Layer-to-layer via structures are almost always used in PCB designs. These common structures…
- 11 Jun 2013
Verification: DAC 2013 – System Design on Wednesday, June 5th

fschirrmeister

The DAC exhibition comes to a close today, and we have another day with great presentations related to the Cadence System Development Suite. If you want to follow along the flow of our core engines from virtual through RTL simulation, acceleration...
- 5 Jun 2013
Verification: DAC 2013 – System Design on Tuesday, June 4

fschirrmeister

We had a great day on system design yesterday, followed by great party at Austin City Limits with "Asleep At The Wheel" and the EDA band around Jim Hogan. Today shapes up to be just as great! We started early today at 8:00am with our ...
- 4 Jun 2013
Verification: Accelerating Time to Market with ARM Software Development Tools and the Cadence System Development Suite

jasona

In one of the Monday presentations at the Cadence DAC Theater, Ronan Synnott from ARM talked about how ARM Software Development Tools such as DS-5 interact with the Cadence System Development Suite. I thought it would be good to provide a more detail...
- 3 Jun 2013
Verification: How Can You Continue Learning About Advanced Verification at Your Desk?

umery

How much time do you spend "playing" and "learning" before you try a new EDA tool, feature, or flow?
Do you really take a training class and sift through the documentation or books about the subject before you start project work? Or are you the type who has the knack of figuring things out on your own by taking a deep dive, head first?
Learning is an iterative and repetitive process. Human beings spend…
- 3 Jun 2013
Verification: DAC 2013 – System Design on Monday, June 3rd

fschirrmeister

The first day of DAC starts off today with four great presentations on system design at our DAC Theatre. Freescale will present on their use of FPGA-based prototyping, AMD will show their enhanced use of Palladium together with TLM models, ARM wil...
- 3 Jun 2013
Verification: Welcome to DAC 2013!

jasona

I just arrived at DAC 2013 in Austin, and as always I'll be writing about the interactions of software and hardware. This is the 50th DAC, and about 20 years of DAC for me. Although I have not been to every DAC over this ...
- 2 Jun 2013
Verification: Introducing UVM Multi-Language Open Architecture

Adam Sherer

The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e, SystemVerilog, SystemC, C/C+, and other languages into a cohesive verification hierarchy and runs on multiple simulators. Moreover, the new solution is open for additional collaboration and technology enhancement.
Since Cadence introduced ML verification four…
- 31 May 2013

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