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While I suspect that many of our customers have used or heard about the CheckSysConf utility, there may be a few that have no idea how it can help them determine potential Cadence software problems before contacting Cadence Customer Support. More important, CheckSysConf provides information on how to resolve OS/patch issues.

CheckSysConf is a tool that verifies whether the machine on which you want to run the Cadence tools…

When people ask you what you do for a living, is your response as clumsy as mine?  "Um, you see, well I uh, work for this company that sells software that helps people design computer chips?" is typically what I say.  I sometimes say "I'm an Applications Engineer for Cadence Design Systems," and leave it at that.  Either way, the reaction seems to be about the same- the person I'm talking to quickly…

At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. STA compensates for this variability…

Just finished packing for a quick trip to Southern California to help kickoff a round of "techtorials" on Coverage-Driven Verification (CDV) this coming week.  (Thus, in a real sense I'm going out help see that the goodness of CDV I described in my last post is communicated in a very direct way!)  Specifically, in Cadence-speak, a techtorial is a 1/2 and 1/2 mix of seminar-style technical training from an…

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design, I wrote about the concept of a co-verification engineer. It's the very last section of the book. Although a lot of people told me they read the book (and some actually learned something from it), nobody ever contacted me and said they were a co-verification engineer, so I'll ask again in a slightly different way in 2008.

For many years…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various methods for generating schematic plots into the PDF format. Some have purchased tools, others have bundled together free utilities with custom scripts to accomplish the task. Most have not been able to produce the exact desired content, let alone an intelligent PDF plot.

About two years ago, the SPB R&D and Marketing teams developed not…

So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A couple of questions to consider before starting are:

What parameters do you want to measure?
What types of test benches are required to measure these parameters?

Let’s start by considering how to measure the ft of a transistor, ft is a standard figure of merit used by analog…

In an announcement concurrent with Semicon West 2008, Shocking Technologies has announced their Cadence Connections membership.  Take a look at the announcement and find out more about how Cadence Allegro PCB and Package designers can benefit from Shocking's rules and materials to safeguard their products from electrostatic discharge (ESD) dangers.

http://www.shockingtechnologies.com/pdf/Shocking_Cadence_Press_Release…

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in creating and re-using system-on-chip IP.  C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. 

C-to-Silicon Compiler automatically translates and optimizes abstract behavioral…

Inductors, transformers and transmission lines are critical components in any high frequency integrated circuit. Conventional electromagnetic tools used for the design of these components are difficult to setup, require electromagnetic expertise and are not integrated in IC design flows.

Traditionally, specialized modeling teams work hard for several months to design, fabricate and characterize a limited set of inductors…

Hello and welcome to the new Cadence community site, and my first blog post. You will see me here from time to time posting on topics and trends in the Power Efficient Design and Low Power Design area -- and most importantly, how we as a community can play a bigger part in ensuring your success.
 
If you have any topics you would like to see me cover, please feel free to leave a comment or send me a private message.

For my…

What's Good About Differential Pair Support in ASA?

Quite a bit actually!

In the SPB16.0/SPB16.01 release of the Allegro System Architect (ASA) product, there were several new features added for Differential Pair Support. You can certainly read the details in the new Cadence Help utility (which is also new and improved in the SPB16.0 release), but here are some highlights -

• Setup options for identifying user…

The EDA industry been doing system level design and verification for years; we just haven't been doing it very well.  Most all of us do hypothesize about what might be the ideal configuration of hardware and software to deliver our application in a cost effective way.

However, becuase there are so few tools we can use to test our hypothesis, we are soon reduced to taking a leap of faith in to commit to a particular…

Verification consultant Brian Bailey recently started blogging for Chip Design Magazine. One of his first posts was to define verification. He did a great job and I encourage people to read over what he wrote.

What you realize when you read his post is that verification is not directly related to two other topics that are often discussed as part of verification. These topics are important to verification, but are not verification…

Greetings!

My name is Steve Lewis and I'm a product marketing director working in the custom design area within Cadence. 

I thought I'd kick off this blog with a brief introduction. I've been with Cadence for almost 18 years, with three years additional experience working at Daisy CAE systems, a pioneer in the EDA field.

This blog will cover a wide range of topics related to analog and custom digital design…

Ordinarily chaos is bad thing.  Yet like it or not, the world your SoC lives in is in complete chaos -- your chip will see all sorts of unexpected stimuli and unimagined use cases over time, which can lead to end users finding the bugs you missed.

The most frequently viewed forum post in the old cdnusers.org "Digital IC->Floorplanning, Place and Route" forum initially started off as a seemingly simple inquiry: "Can CTS Stop Tracing on Hierarchical Module Ports?"

From that one question came a number of suggestions and discussion about using First Encounter (FE) Clock Tree Synthesis (CTS) LeafPin and LeafPort constructs and whether they could…

With all of the press and interest from customers adopting it, I am sure most of you have heard about the OVM (Open Verification Methodology), which is jointly developed and supported by Mentor Graphics and Cadence.  If you haven't heard about the OVM, you can check out the OVM World site to read all about it.

The main focus of the OVM so far has been on providing a testbench methodology and class library for SystemVerilog…

It has been said many time that SPICE, the analog engineers tool of choice, is virtually the same as it was 20 years ago, while digital engineers have been happily zooming up the evolutionary chain. There have been a number of attempts to prod analog designers into closing the gap with the introduction of behavioral modeling languages, and more abstract system modeling solutions. However, they are not widely adopted…

At the recent Design Automation Conference (DAC) in Anaheim, Calif., Cadence did not have a big booth but we were involved in many different activities. The most fun for me was the first "OVM World Summit" -- a meeting for users of the Open Verification Methodology (OVM). Cadence co-sponsered the event, which drew more than 70 attendees from a wide range of companies.

After introductions, three hands-on OVM…

There's a great issue of Xrosstalk magazine out there that talks about algorthmic modeling for high speed SerDes channels.  Cadence as well as other EDA companies give their take on the subject. 

Here's a link to the articles:

http://www.xrosstalkmag.com/images/magazine/xrosstalk_magazine_june08_final.pdf

What are your thoughts?