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There are several new enhancements associated with the 16.6 PCB SI Channel Analysis (CA).

Read on for more details …

SigXplorer has been enhanced to provide greater flexibility associated with AMI model management. Experimentation with buffer and AMI combinations, until this release, required joining them at the library level. No manipulation could be done in SigXplorer. Now, the 16.6 release provides canvas-level…

In both previous coverage blog posts (Part I and the Part II), we showed two solutions for refining instance-based coverage in a reusable way. And in doing so, we demonstrated a case where using the instance_ignore option is more suitable than using the extension under when solution.

Now, let us modify the requirement a little, by adding a new item to the covergroup:

extend packet_generator{

  cover packet_generated…

The Shape - Add Rectangle command has been enhanced in the 16.6 Allegro PCB Editor release to support cornering options of ‘Chamfer’ and ‘Round’. Control the corner length/radius using either ‘Explicit Length’ values or as a ‘Percentage of the Short Edge’. When adding a rectangular shape, you have the option to interactively draw the rectangle or add parameterized shapes using the new Place Rectangle option. …

In the last coverage blog, we showed how the extensions of covergroups under when subtypes can help us write a reusable per-instance coverage.

We described a test case where a packet generator unit can create packets of different sizes. The packet generator unit has a field that describes the maximum size of any packet that can be generated by the packet_generator instance:

type packet_size_t: [SMALL, MEDIUM,LARGE,HUGE];

Verification regression consumes expensive compute resources and precious project time, so any speed-up has both a technical and business impact. As announced July 17, Fujitsu was able to improve both the compute resource and project time by using Cadence Incisive products and working closely with Cadence field resources to deploy them.  Results:  1.5x faster per test, 3x faster regression overall, and 30x storage reduction…

• CPM Explorer
  • Viewing project .cpm data
• Progress Controls
  • Locking/unlocking flow steps
  • Manual advance
  • Access controls – who can access flow steps
• Customizations
  • Changing the welcome page
  • Adding a corporate look and feel

After talking about some tips for using trace files in debugging Verification IP simulations in my last blog post, here I am back again, as promised. This time I'll discuss and provide references for the Denali Migration Guide, NVMe PureView VIP Usage, Verification Flow for USB, Instantiating VIP Models with SystemVerilog, and finally Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP.

1. Many users have reported…

Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed-Signal/Low-Power Focused Technology-On-Tours to Penang and Singapore later in July 2013. Cadence will showcase mixed-signal and low-power solutions aimed at designs that cater to the always connected world. With smart devices taking over our everyday lives, design teams are moving towards complex mixed-signal designs with advanced low power…

Wow!  There was an amazing amount of new content added last month.  A lot of new videos and some Really Useful articles.  Enjoy.

Rapid Adoption Kits

1. CPF-AMS Low-Power Mixed-Signal Simulation

CPF-AMS is an extension of mixed-signal simulation to help the designer simulate mixed-signal low-power design with the CPF language. It includes all CPF-related technology applicable in the mixed-signal world, such as power shut off…

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an easy-to-use and more flexible method of connecting schematic symbols in complex designs using the concept of bundling and connecting signals/nets.

What are NetGroups

A NetGroup is a heterogeneous collection of nets. A NetGroup can have scalars (wires), vectors (buses), or a combination of both scalar and vector nets. It can also have other…

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers, devices and transaction types. Cadence VIPs also support integration and traffic generation in all popular verification environments.

During the past year, I have seen engineers struggling with debug for VIP based simulations…

If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across…

• Rules file can be added via the Component Browser as Real Interfaces
• FPGAs can be linked to corporate symbols/footprints
• Virtual Interfaces can be converted to Real Interfaces
• FSP generated symbols can be customized as split symbols
• Pin directions for generated symbols can be customiz…

The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements to the Find command.

You can now:

• Search for a property with a specific value
• Use regular expressions for matching values
• Use global find and replace for offpage connectors

Read on for more details…


In earlier versions of Allegro Design Entry CIS (Capture/Capture-CIS) you could only search for strings and if they matched in property…

Verification is the art of modeling complex relationships and behaviors. Effective model creation requires that the verification engineer be driven by a curiosity to explore a design's functionality, anticipate how it ought to work, and understand what should be considered an error. The model must be focused and expressed as clearly as possible, as it transitions from a natural language to a machine-understandable…

I had the great opportunity to represent Cadence at the Design Automation Conference (DAC) at Austin a few weeks back. In my role as a Mixed-Signal Solutions evangelist at Cadence, I was thoroughly amazed by the excitement from the ever growing design community at this year's DAC. For Cadence, this was an excellent opportunity to showcase the various technologies covering system, IP and SoC designs.

A common theme…

The complexity of the designs is constantly increasing and more and more logic is being placed inside hierarchical blocks. This leads to an increase in the number of interfaces that are exposed by the hierarchical block. The increased number of interfaces means more pins are required on the block symbol. In many cases, the block symbols become so big (e.g. FPGAs, large pin count devices) that they cannot be placed on a 

Let me start this entry on a bit of a personal note. As a Pole, I was very happy to learn some time ago that the 2013 European meeting of the MIPI Alliance would take place in my home country. Later, it turned out that Cadence was to acquire the IP business of Evatronix, the company I worked at. These events ended up taking place one right after another—on Thursday, June 13, Cadence completed its acquisition of…

The evolution of signal integrity analysis is similar to many electronic design tasks.  First, best practices were followed. Second, analysis tools were used to verify final designs. Then, to reduce design re-spins, what-if analysis techniques were created to drive constraints that could then be verified at the end of the design cycle.

 Because of tight schedules and time to market pressure, there is often little time…