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Static electricity can send shocks through your body.  We have all experienced walking across carpet on a dry day and then touching a metal doorknob.  This shock discharge is formally known as Electrostatic Discharge (ESD).  ESD can be annoying to us on a dry day or when wearing nylon clothing, but it can be much more serious to electronic devices.  When the current associated with what may seem like a harmless shock enters…

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence.  Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production.  In this interview on the floor of the Design Automation Conference (DAC 2012), Mike gives a brief snapshot of how innovations in debug automation have moved from the lab to the show floor, and…

In this blog post I want to highlight the command get_metric that was introduced in Encounter Digital Implementation (EDI) System 10.1 and enhanced further in version 11. Have you ever tried writing a script to extract information from the log file like run times or timing results? It becomes complicated quite fast when you're trying to capture the desired data, especially if a command is run multiple times. Also, any script…

Continuing our conversation on leveraging social media for EDA, at the Design Automation Conference (DAC 2012) I had the honor of interviewing again with EETimes editor Brian Fuller -- this time the focus of the conversation was on video. Specifically  we talked about which video formats have proven to be most popular, and which are most effective for delivering complex technical information.

To play the video, click on…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners at Oski Technology tackled a truly unique challenge. To show off their formal verification prowess they took an IP block from NVIDIA sight unseen  (actually, on Sunday evening before the DAC they received a spec and a 15 minute briefing) and over the course of 72 hours from Sunday at 5pm to Wednesday at 5pm they used Incisive Enterprise…

Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs.  Get it wrong and/or miss a bug in the bypass logic and whole system can simply freeze. 

Fortunately, the 2012 DAC User Track Best Presentation award-winning paper titled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full…

• Select multiple parts or models
• Edit-All
• Check-out
  • Edit property values in list
  • Add new part rows
  • Edit linked…

In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC 2012).

Verification momentum - I grant that I might be influenced by some amount of selection bias, but I could swear that this year there was way more interest and vendor presence in the functional verification space than at recent DACs.  Our…

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.

Martin Lund, Senior Vice President at Cadence, was recently interviewed at DAC2012 by EE Times’ Brian Fuller. Martin laid out a vision for commercial…

There are two ways in e to define an event to be sensitive to a change of value in the simulator:

1. Use simple_port and bind it to the HDL object. Then create an event that will be sensitive to rise/fall/change of that port value with the @sim sampling event:

sig_p : inout simple_port of bit is instance;

keep sig_p.hdl_path() == "sig";

event sig_e is rise/fall/change (sig_p$)@sim;

2. Use an event_port and define…

In the 16.5 Design Entry HDL (DEHDL) release, Object Visibility Layers are introduced. The different objects in DEHDL are now available on different layers and you are provided a toolbar for which the visibility of each of object layer can be controlled. This is similar to displaying layers of objects in Allegro PCB Editor.

Read on for more details …

The different DEHDL object types available are:

1. Components/Sym…

As clock and data frequencies increase and high-speed systems become more densely populated, noise-free power delivery becomes a major challenge for PCB design. When fast switching devices change state simultaneously, power flow ripple propagates through the power delivery system as noise that varies with frequency. This noise can, in turn, disturb surrounding high-speed devices.

To ensure that high-speed systems continue…

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here. Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and stability of the SystemVerilog library.

Building on a decade of experience with the methodology, Cadence offers a unique solution for the UVM. You can see more about the unique…

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved…

Querying the Encounter database with dbGet is typically pretty concise to begin with. But you might not be aware of its support for expression-based matching, which enables even more compact scripting.

Let's take a very simple but common scripting challenge: Finding all of the high fanout nets in the design.

Then let's take this a little further. How would we write a script to find all nets with fanout greater than…