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Breakfast Bytes: Formal Signoff with JasperGold

Paul McLellan

At the recent Jasper User Group, I said that there were several themes. For overall coverage of the event, see my post Jasper User Group 2018. One was post-silicon debug, which I wrote about in the post Formal Post-Silicon Debug. Another theme w...
- 29 Oct 2018
Breakfast Bytes: Sunday Brunch Video for 28th October 2018

Paul McLellan

https://youtu.be/1vU3sg3QlWc Coming from building 8 lab (camera Sean) Monday: The World's First Working 7nm 112G Long Reach SerDes Silicon Tuesday: Arm TechCon: Get Ready for the NEOVERSE Wednesday: ERI: Hardware Security Work...
- 28 Oct 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之9：新设计规则检查

TeamAllegro

Allegro PCB 17.2-2016发行版增强了钻孔相关功能我们为实际的钻孔工具、背钻工具、方形孔、沉头孔等增加了焊盘定义，并增加了钻孔容差。应广大用户需求，背钻位置现在完全支持DRC间距规则。（见升级到Allegro17.2-2016的10大理由之4：行业领先的背钻能力）。同时更新的还有标准钻孔间距DRC的行为变化。追溯到16.2版本，我们提供了钻孔DRC来支持 “内层无盘工艺” 功能。该检查功能只有在焊盘被删除、或者焊盘尺寸比钻孔小时（测位焊盘）才有效。从那以...
- 26 Oct 2018
Breakfast Bytes: ERI: CHIPS and Chiplets

Paul McLellan

One of the DARPA programs that is part of the Electronic Resurgence Initiative (ERI) is called CHIPS. This stands for Common Heterogeneous Integration and IP Reuse Strategies. In fact, the CHIPS program started before ERI existed, so I'm not enti...
- 26 Oct 2018
Verification: Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High Performance Computing Servers

XTeam

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based high-performance computing (HPC) server environments. Now, all of the Cadence verification software tools you know and love—including Xcelium Simulator—can be run on the Hewlett Packard Enterprise (HPE) Apollo 70 system, which uses…
- 25 Oct 2018
Analog/Custom Design: Virtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit

Arja H

The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has been updated for IC6.1.8/ICADVM18.1 to cover the new features. These include Setup Library Assistant Worst Case Corners in Run Plan Minor usability improvements
- 25 Oct 2018
The India Circuit: An Ocean Of Opportunity

Madhavi Rao

We were lucky to have Cadence CEO Lip-Bu Tan visit India recently, when he keynoted at CDNLive India. Lip-Bu always has interesting insights. He has always been very positive about the future of the semiconductor industry, and this year was no differ...
- 25 Oct 2018
Breakfast Bytes: Formal Post-Silicon Debug

Paul McLellan

Two outstanding presentations at the recent Jasper User Group were on using JasperGold (JG) for post-silicon debug. The two presentations were from Laurent Arditi of Arm, In Case of Emergency Call 1-800-FORMAL and from Jim Kasak of HP Enter...
- 25 Oct 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Cadence Unveils 112G Long-Reach SerDes IP in 7nm Technology

References4U

With hyperscale datacenters requiring network switches delivering bandwidths of 12.8 Tbps and beyond, there is strong demand for 112G SerDes IP for the underlying ASICs and SoCs. In this week’s Whiteboard Wednesday, Wendy Wu explains the high-performance networking market drivers and introduces the Cadence® 112G Long-Reach SerDes IP implemented in 7nm process technology.

www.youtube.com/watch
- 24 Oct 2018
Breakfast Bytes: ERI: Hardware Security Workshop

Paul McLellan

The opening morning of DARPA's Electronic Resurgence Initiative summit in San Francisco consisted of several workshops, called "What's Next Workshops". I picked the hardware security workshop since the DoD cares more about security ...
- 24 Oct 2018
System, PCB, & Package Design : How To Maintain Connectivity in a Multi-Board PCB System

TeamAllegro

Today’s electronics often incorporate multiple interconnected printed circuit boards (PCB) into their designs. Getting all the components in a multi-board system to work together as a cohesive final product hinges on choosing the right connectors for the design. In this post, we’ll dive into the different types of PCB interconnects and some best practices for implementing them in your next multi-board PCB project.
- 23 Oct 2018
Breakfast Bytes: Arm TechCon: Get Ready for the NEOVERSE

Paul McLellan

I don't know if it was the vibe Arm's marketing was going for, but if you wanted to evoke The Matrix without infringing any copyrights, The NEOVERSE does the trick. It's hard to believe but The Matrix will be twenty years old next ye...
- 23 Oct 2018
Breakfast Bytes: The World's First Working 7nm 112G Long Reach SerDes Silicon

Paul McLellan

At the start of November last year, Cadence announced that it was acquiring nusemi, a company focused on the development of high-speed SerDes interfaces. Today, Cadence demonstrated working 7nm SerDes testchips running at 112 Gbps. It ...
- 22 Oct 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之8：过孔结构——下一代高速布线解决方案

TeamAllegro

过孔转换对信号布线来说十分常见。在高速设计中过孔转换是造成PCB互连中信号衰减的主要原因。而且高速通道需要地孔临近关键信号，在信号走线换层时，提供连续的回流路径，来降低信号损耗。（点击查看大图） space 如果您是一位PCB设计工程师，您会非常清楚，实现符合需求的布局布线很复杂、很花时间。现有的方法常常是手动的、冗长的，容易造成布局布线错误或丢失。我们很容易忘记在关键信号添加回流孔，或者移除关键信号走线之后遗留下的回流孔。此外，布线换层时，在高速差分对周围添加定制的过孔也是非常繁琐的手动过...
- 19 Oct 2018
System, PCB, & Package Design : How is a Multi-board PCB System Assembly Different from Rigid-Flex Assembly

TeamAllegro

When people typically think of multi-board PCB design, they tend to picture racks of boards in server farms or the components of a gaming rig. But what if your typical rigid boards don’t fit within the physical envelope of your multi-board application? Do you pay a premium for flexible circuitry? What if you could have the best of both worlds?
- 19 Oct 2018
Breakfast Bytes: The DARPA Electronic Resurgence Initiative (ERI)

Paul McLellan

Many weeks ago DARPA organized a summit at the Palace of Fine Arts in San Francisco. The first day consisted of a workshop and some other presentations, including one by Cadence's Tom Beckley. Since Tom's presentation was very similar to what he...
- 19 Oct 2018
Analog/Custom Design: Virtuoso IC6.1.8 and ICADVM18.1 Now Available

Virtuoso Release Team

The IC6.1.8 and ICADVM18.1 production releases are now available for download. To find out what new and enhanced features have been introduced, click here…
- 18 Oct 2018
Breakfast Bytes: CDNLive Israel 2018

Paul McLellan

This week it was the last CDNLive of the year, CDNLive Israel in Tel Aviv. From my point of view the show ran perfectly. But I'm always reminded of that description of a swan as "serene on top and furiously paddling underneath." I reali...
- 18 Oct 2018
Breakfast Bytes: Jasper User Group 2018

Paul McLellan

This week it is CDNLive Israel. But last week it was Jasper User Group (JUG). At it happens, Jasper was one of the early companies to sign up with SemiWiki when we started it, so I've been going to Jasper User Group for longer than either I'v...
- 17 Oct 2018
Digital Design: What's in it for Me in Innovus 18.10 Release?

MJ Cad

At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through various features, including its full-flow massively parallel architecture. Innovus 18.10 release takes all these benefits even further. In this blog, I will start with…
- 16 Oct 2018
Breakfast Bytes: Of Arms and the Man I Sing

Paul McLellan

Arma virumque cano—of arms and the man I sing. This is the famous opening line of Virgil's Aeneid, the curse of many a schoolboy's Latin learning days, mine included. Anyway, the reason for all this talk about arms (Arma) is that today is ...
- 16 Oct 2018
Verification: Learn How Valens uses Specman Macros Automate Configuration of Verification Environments at DVCon EMEA Next Week

Steve Brown

Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the verification environment to their design. This saves them effort and lowers the learning curve for engineers who jump from project to project. In collaboration with Veriest Verification Ltd, a Cadence Connections Verification partner…
- 16 Oct 2018
System, PCB, & Package Design : Real World (Unexpected) Examples of Multi-Board PCB Systems

TeamAllegro

What do reusable rockets, self-driving cars, and the blockchain have in common? Besides breaching major milestones in the last 3-5 years, they are all stellar examples of how advancements in multi-board printed circuit board (PCB) design is propelling us into the future. In this post we’ll look at how advances in multi-board PCB systems are helping push the boundaries of spaceflight, autonomous vehicles, and the blockchain…
- 16 Oct 2018
Breakfast Bytes: DDR5 Is on Our Doorstep

Paul McLellan

The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the f...
- 15 Oct 2018
Breakfast Bytes: ESD Alliance Workshop on Digital Marketing: Tools and Sales

Paul McLellan

Yesterday was the first part about the ESD Alliance Digital Marketing workshop. Today, it is part 2 (of 2). Nicolas Part 2: Training and Tools Today's marketers need to be hands-on since there are a lot of different aspects and it is too slow (no...
- 12 Oct 2018

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