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Breakfast Bytes: MEMS Design Competition: The Envelope Please...

Paul McLellan

The Cadence Academic Network sponsored a MEMS design contest over the last couple of years. At CDNLive EMEA 2018, the winners were announced. The idea was to encourage groups to design using a mixture of the Cadence analog/mixed-signal design tools, ...
- 23 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - The Truth about Designing for Automotive Functional Safety

References4U

In this week’s Whiteboard Wednesday, Tom Hackett challenges conventional wisdom and concludes that achieving functional safety means going beyond the letter of the law of ISO 26262 to embrace the spirit of a functional safety culture.

www.youtube.com/watch
- 22 May 2018
Breakfast Bytes: Accelerating AI: ...Present and Future

Paul McLellan

Yesterday I wrote about the first part of Krste Asanović's presentation Accelerating AI: Past, Present, and Future. Although yesterday's post only covered the past. Today, it's time for the present and future. Graphics Processing Units GP...
- 22 May 2018
Breakfast Bytes: Accelerating AI: Past...

Paul McLellan

SiFive does a quarterly series of tech talks, not necessarily directly to do with SiFive or even RISC-V. For example, last quarter it was Paul Kocher (and if you don't know that name, you need to go and read my post about that talk Paul Koc...
- 21 May 2018
Breakfast Bytes: CGTN China 24 Interview

Paul McLellan

https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week, being interviewed about the Chinese Semiconductor Industry. www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email.
- 18 May 2018
Analog/Custom Design: Virtuosity: What's New in Run Plan – Part II

Yagya Mishra

The Run Plan assistant in Virtuoso ADE Assembler has proved to be one of the most popular features. It provides the capability to create multiple variations of the setup within a single session, each of these runs has their own setup details that override the settings in the active setup. Simulations can be run for all the runs defined in the run plan with a single click. If there are no dependencies, the results are…
- 18 May 2018
Breakfast Bytes: Achronix Grew 700% Last Year...eFPGA is a Thing

Paul McLellan

I don't normally write about the FPGA market. There are three reasons for this. First, Cadence doesn't participate in the market for FPGA tools (for FPGA users. I'm pretty sure the arrays themselves are almost all designed on Virtuos...
- 18 May 2018
Breakfast Bytes: CDNDrive: ISO 26262...Chapter 11

Paul McLellan

At CDNLive EMEA Robert Schweiger laid out his perspective on the automotive market. At April’s CDNLive Silicon Valley too, but as you might guess from his name, Germany is his home. Sanjay Lall, the head of Cadence EMEA, had told me the day bef...
- 17 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - An Introduction to Compute In-Memory

References4U

In this week’s Whiteboard Wednesday, Marc Greenberg introduces the concept of “Compute In-Memory” - a hot topic which promises to greatly improve the performance of memory transactions while reducing energy. However, there are alternate approaches that can accomplish the same goals with today’s technology. This video explores the approach and alternatives.

https://youtu.be/61J2R42yAzQ
- 16 May 2018
Breakfast Bytes: TSMC: Mobile, HPC, IoT, Automotive...and Packaging

Paul McLellan

This is the third post about the TSMC Technology Symposium that was held on May 1st. The first two are TSMC Technology Symposium 2018 and TSMC's Fab Plans and More. In the afternoon, there were four presentations: Doug Yu on Advanced Packag...
- 16 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 21st to 25th 2018

Paul McLellan

https://youtu.be/AmlYRYzIHtY Coming from my office (camera Sean, guest star Alexa) Monday: Accelerating AI: Past... Tuesday: Accelerating AI: ...Present, and Future Wednesday: MEMS Design Competition. The Envelope Please Thursday: The...
- 15 May 2018
The India Circuit: Inspiration, Networking and Food For Thought

Chandrika Durbha

Recently I had the opportunity to attend the Society of Women Engineers (SWE) Conference in Pune, India. But before I get into talking about the Conference, I want to tell you about an incident that got me thinking. While in Pune, I visited my ...
- 15 May 2018
Breakfast Bytes: CDNLive: Testing Times in Munich

Paul McLellan

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning, or parallel simulation get all the attention. But a chip doesn't only have to be manufactured, it also has to be tested. At CDNLive EMEA I met Erik Jan Marinissen o...
- 15 May 2018
Academic Network: Status of Verification Education in Academia

Anton Klotz

Since I’ve started working for Cadence Academic Network three years ago, when talking to big Cadence customers sooner or later they mention the verification topic. The need for verification is increasing, the demand for verification experts is ...
- 14 May 2018
Breakfast Bytes: Agile Development of Custom Hardware

Paul McLellan

It was back in 2016 that I first heard about RISC-V, and the Raven implementation, and the Chisel hardware design language that Berkeley had developed. See my post A Raven Has Landed—RISC-V and Chisel. The thing that was most impressive wa...
- 14 May 2018
Breakfast Bytes: Compromising a Fortune 500 Company...Without Hacking a Thing

Paul McLellan

Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important social engineering has become. For example, Ubiquity Networks lost $39M in 30 minutes through social engineering. Whoever took the money targeted the company&#...
- 11 May 2018
System, PCB, & Package Design : Power-Aware SI DDR4 Simulation: You Have a Choice!

Sigrity

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO) has been a hot topic for decades in signal integrity (SI) circles (see figure to the right). Some claim only a SPICE simulation using transistor-level models can...
- 10 May 2018
Breakfast Bytes: CDNLive EMEA, Driving to the Future

Paul McLellan

This week it has been the 13th European CDNLive, held in Unertschleißheim in the suburbs of Munich. The event starts on Monday afternoon with some technical tracks. The big day is Tuesday, starting with the keynotes, and then going to a full p...
- 10 May 2018
System, PCB, & Package Design : Make Reliable Designs That Won’t Fail In The Real World!

Ronak Shah

Heard about the ongoing recalls in the Automotive and Cellphone industry? Let's address the important issue of Circuit Reliability!
- 9 May 2018
Breakfast Bytes: Digital Marketing in EDA...with No Hands on the Wheel

Paul McLellan

Years (decades) ago, Robert Townsend, the CEO of Avis, faced a problem. Hertz was several times as big as Avis. Avis was losing money. He asked the Bill Bernbach, the head of his advertising agency DDB, how he could effectively get $2 of advertising...
- 9 May 2018
Whiteboard Wednesdays: Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard

References4U

In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface Group, describes the new DFI 5.0 specification and the enhancements it provides to the Controller/PHY Interface of DDR memory channels.

https://youtu.be/5rfxkt-5T4o
- 8 May 2018
Breakfast Bytes: Legato: Smooth Reliability for Automobiles

Paul McLellan

In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that EDA would "probably not" solve the problems of automotive, since they are totally focused on the leading-edge nodes. Well, that was four years ago, and EDA has got autom...
- 8 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 14th to 18th 2018

Paul McLellan

https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy Le) Monday: Agile Development of Custom Hardware Tuesday: CDNLive EMEA Session Wednesday: TSMC: Mobile, HPC, IoT, Automotive...and Packaging Thursday:&...
- 7 May 2018
Breakfast Bytes: TSMC's Fab Plans, and More

Paul McLellan

The TSMC Technology Symposium took place recently. I grouped all the process and packaging roadmap into my previous post TSMC Technology Symposium 2018. Today I'll look at the rest of what was presented in the morning. Subsequently I'll put t...
- 7 May 2018
Breakfast Bytes: TSMC Technology Symposium 2018

Paul McLellan

This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president of TSMC North America was the MC for the day. Dave kicked off by giving a few statistics about TSMC's business in North America. In Q4 last year, North Ameri...
- 4 May 2018

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