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Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL

By Rick Sanborn | 20 Jul 2020

The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process of SV UVM testbench reuse in the AMS UNL flow. Continue reading to know more.

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SystemVerilog | AMS | uvm | Functional Verification | mixed signal methodology | AMS Designer | Mixed Signal Verification | Unified Netlister | SV-RNM | SVA | analog/mixed-signal | assertions | mixed signal | mixed-signal design | MDV | AMS Verification | mixed-signal verification | verification
Start Your Engines: The Blog-o-Meter Check

By Jommy | 2 Jul 2020

A summary of the blogs published in the Start Your Engines blog series.

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CLIPS | mixed signal design | Functional Verification | AMS Designer | Unified Netlister | AMSD Flex Mode | mixed-signal verification
Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC Verification

By Lalit Mohan | 18 Jun 2020

Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel.

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mixed signal design | mixed-signal methodology | AMS Designer | analog/mixed-signal | Virtuoso | axum | mixed signal | avum | mixed-signal verification
Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional Verification Flow

By Rick Sanborn | 4 Jun 2020

What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made possible with the latest Xcelium Mixed-Signal technologies from Cadence.

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AMS | mixed signal design | AMS Designer | mixed signal solution | Verilog-AMS | analog | analog/mixed-signal | Virtuoso | RNM | wreal | AMS Verification | mixed-signal verification | verification
Start Your Engines: The Why and How of Generating Spectre Netlists for Analog Blocks Using UNL

By Qingyu Lin | 21 May 2020

Read to know about generating netlist in the Spectre native format using AMS UNL.

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AMS Designer | Unified Netlister | analog/mixed-signal | mixed signal | AMS UNL | mixed-signal verification
Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!

By Andre Baguenier | 30 Apr 2020

This blog talks about how to enable the AMS Designer flex mode.

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mixed signal design | AMS Designer | AMSD | AMSD Flex Mode | mixed-signal verification
Start Your Engines: AMSD Flex—Take your Pick!

By Qingyu Lin | 16 Apr 2020

Introduction to AMSD Flex mode and its benefits.

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mixed signal design | AMS Designer | AMSD | AMSD Flex Mode | mixed-signal verification
Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods

By msteam | 21 Feb 2019

Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These...

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AMS | Virtuoso Schematic Editor | Low Power | virtuoso power manager | Virtuoso-AMS | mixed signal design | mixed signal solution | Virtuoso | low-power design | mixed signal | mixed-signal verification
Take Advantage of Advancements in Real Number Modeling and Simulation

By msteam | 26 Feb 2018

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor...

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real number modeling | analog | Mixed-Signal | RNM | mixed-signal verification
Integrating AMS IP in SoC Verification Just Got Easier

By msteam | 6 Feb 2018

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations. But, what about...

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AMS | mixed signal solution | Mixed-Signal | analog/mixed-signal | Virtuoso | mixed signal | Virtuoso environment | mixed-signal verification
Automatically Reusing an SoC Testbench in AMS IP Verification

By msteam | 4 Jan 2018

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently...

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AMS | mixed signal design | mixed-signal methodology | mixed signal solution | analog | Mixed-Signal | analog/mixed-signal | Virtuoso environment | mixed-signal verification
Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification

By TheLowRoad | 10 Dec 2014

Key Findings : There are a host of issues that arise in mixed-signal verification. As discussed in earlier blogs , the industry trends indicate that teams need to prepare themselves for a more mixed world. The good news is that these top five pitfalls are all avoidable. It’s always interesting to study the human condition. Watching the world through the lens of mixed-signal verification brings an interesting microcosm...

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MS | uvm | Metric-Driven-Verification | Palladium | Mixed Signal Verification | Incisive | MDV-UVM-MS | Virtuoso | mixed signal | MDV
Five Reasons I'm Excited About Mixed-Signal Verification in 2015

By TheLowRoad | 3 Dec 2014

Key Findings : Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it. As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the...

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uvm | mixed signal design | Metric-Driven-Verification | Mixed Signal Verification | MDV-UVM-MS
Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations)

By TheLowRoad | 19 Nov 2014

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase. Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics...

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Advantest | Palladium | Mixed Signal Verification | Emulation | mixed signal
The Elephant in the Room: Mixed-Signal Models

By TheLowRoad | 5 Nov 2014

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome. Without the magical models, the process breaks down for lack of performance, or holes in the chip verification. In the last installment of The Low Road , we were at...

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metrics-driven methodology | real number modeling | uvm | CPF | RNM | UPF | mixed signal | MDV | verification
It’s Late, But the Party is Just Getting Started

By TheLowRoad | 30 Oct 2014

Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed. The Cadence party for mixed-signal verification is the hottest ticket in town. With some important public events now behind us and more on the horizon, the agendas make it clear that there is mounting pain in the realm of verifying...

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AMS | analog behavior | AMS-Designer | AMS Designer | analog behavioral models | analog/mixed-signal | AMS Verification
How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your Desk?

By SumeetAggarwal | 30 Apr 2014

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the system-on-chip (SoC) level. But today's mixed-signal designs have multiple...

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real number modeling | AMS Designer | EDA training | SV-RNM | DMS | mixed signal | Schematic Model Generator | RAKs
Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

By DeveshJain | 10 Dec 2013

Why is There a Need for Low Power Solutions? With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these electronic chips have also greatly increased. There has been a surge in the production of portable devices like mobile phones, laptops, tablets, and game boxes that support multiple applications and use various multimedia...

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Low Power | mixed signal design | mixed-signal methodology | mixed signal solution | CPF | LVS | cdl | Schematics-XL | Mixed-Signal | analog/mixed-signal | Virtuoso | mixed signal
IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

By AndreasLenz | 29 Oct 2013

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs. What's new in Virtuoso IC6.1.6? VSR routing engines were enhanced to improve routing quality (QoR) and to give better...

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Technology on tour | MS ToT | VSR | mixed-signal ToT | mixed-signal training | Router | tech on tour | Open Access | analog/mixed-signal | OA: OpenAccess | tech-on-tour
Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community

By Sathish Bala | 6 Oct 2013

If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring one's knowledge to another person instantly). Mixed-Signal Technology Summit , Oct. 10 at Cadence's San Jose campus, is the closest thing to a mind meld to share mixed-signal design practices and challenges among the design...

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IP | cadence | AMS Designer | SV-DC | Incisive | SV-RNM | DMS | Virtuoso | mixed-signal book | mixed-signal summit | RNM | mixed signal
Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events

By Sathish Bala | 15 Jul 2013

Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed-Signal/Low-Power Focused Technology-On-Tours to Penang and Singapore later in July 2013. Cadence will showcase mixed-signal and low-power solutions aimed at designs that cater to the always connected world. With smart devices taking over our everyday lives, design teams are moving towards complex mixed-signal designs with advanced low...

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conformal | SystemVerilog | EAD | AMS | EDI | Low Power | IP | Penang | Technology on tour | mixed-signal ToT | Cadence events | tech on tour | AMS Designer | behavioral modeling | Encounter Digital Implemenation | Advanced Node | analog | Incisive | Shenzhen | LDE | analog/mixed-signal | Virtuoso | mixed-signal summit | RNM | mixed signal | SMG | Cadence Community | Singapore | verification
OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for Smart Devices

By Sathish Bala | 28 Jun 2013

I had the great opportunity to represent Cadence at the Design Automation Conference (DAC) at Austin a few weeks back. In my role as a Mixed-Signal Solutions evangelist at Cadence, I was thoroughly amazed by the excitement from the ever growing design community at this year's DAC. For Cadence, this was an excellent opportunity to showcase the various technologies covering system, IP and SoC designs. A common theme...

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Solutions | DAC | cadence | Analog-Centric | Austin | Open Access | analog | VDI | Digital-Centric | Virtuoso | digital | oa | Encounter Digital Implementation | mixed signal | Texas Instruments | Mixed-Signal Methodology Book
Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013

By Sathish Bala | 31 May 2013

We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road does get tedious, what kept me excited was the enthusiasm shown among Cadence customers for the Mixed-Signal Tech-on-Tour events. Close to 400 customers attended these Mixed-Signal Tech-On-Tour events. The Dallas Mixed...

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real number modeling | clp | AMS Designer | CPF | Conformal Low Power | DAC 2013 | Mixed-Signal | Virtuoso | Internet of Things | amsDmvmv | mobile | PIEA | mixed signal | wreal | SMG | MDV | Schematic Model Generator | ARM Cortex-M | verification
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

By Sathish Bala | 29 Mar 2013

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face are in SoC level verification and seamless analog/digital implementation. Cadence has been addressing these challenges...

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AMS | EDI | CDNLive | CDNLive 2013 | MS ToT | cadence | tech on tour | mixed-signal IP | AMS Designer | analog | analog behavioral models | analog/mixed-signal | Virtuoso | mixed signal methodology guide | mixed signal | CDNLive SV 2013 | OpenAccess | SoCs | AMS Verification | mixed-signal verification
"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

By Sathish Bala | 25 Feb 2013

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example, with the new line of smart systems, every device or appliance is connected to the Internet to manage their services in a better...

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AMS | DVCon 2013 | CDNLive 2013 | SV-DC | Verilog-AMS | analog | Incisive | Mixed-Signal | smart devices | analog behavioral models | analog/mixed-signal | Virtuoso | Internet of Things | RNM | Verilog AMS | mixed signal | SenseAware | wreal | Virtuoso environment | Schematic Model Generator | mixed-signal verification

Mixed-Signal Design Blogs