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  • Andre Baguenier
    Start Your Engines: Mixed-Signal Modeling Best Practices for Converting a Real Number Signal to Electrical
    By Andre Baguenier | 30 Dec 2020
    In my previous post, I explained the three methods to convert an electrical signal to a real number. In this post, I will cover the methods to convert a real number signal to an electrical signal in your design.
    0 Comments
    Tags:
    R2E conversion | real number modeling | mixed signal design | AMS Designer | Start Your Engines | real to electrical
  • Andre Baguenier
    Start Your Engines: Mixed-Signal Modeling Methods for Converting an Electrical Signal to a Real Number
    By Andre Baguenier | 19 Nov 2020
    This blog explains how to convert an electrical signal to a real number in your design.
    0 Comments
    Tags:
    real number modeling | electrical to real conversion | AMS-Designer | Start Your Engines | analog/mixed-signal | mixed signal | mixed-signal verification
  • Jommy
    Start Your Engines: The Blog-o-Meter Check - Lap 2
    By Jommy | 5 Nov 2020
    This blog summaries the latest five blogs published in the Start Your Engines series.
    0 Comments
    Tags:
    SystemVerilog | mixed signal design | AMS Designer | Start Your Engines | Unified Netlister | Mixed-Signal | low-power design
  • Qingyu Lin
    Start Your Engines: Two Critical Components of Low-Power Mixed-Signal Simulation in AMS Designer
    By Qingyu Lin | 22 Oct 2020
    The low-power format, CPF/UPF/IEEE1801, has been very popular in the digital simulation world for over ten years. Nowadays, it is also commonly used in the mixed-signal simulations.
    0 Comments
    Tags:
    AMS Designer | mixed-signal simulation | Mixed-Signal | low-power design | Connect Module | low power format
  • Andre Baguenier
    Start Your Engines: Speed Up Your Analog Mixed-Signal Verification with Spectre X Simulator
    By Andre Baguenier | 9 Oct 2020
    In this post, I will explain how you could speed up your mixed-signal verification with the Spectre X simulator. I will also cover how Spectre X can be set up for use in the AMS Designer flows
    0 Comments
    Tags:
    spectrex | AMS Designer | universal verification methodology | analog/mixed-signal | axum | mixed-signal design | AMSD Flexible | mixed-signal verification | AMS Flex
  • Andre Baguenier
    Start Your Engines: A GUI to Define HDL Packages for the AMS Designer and SystemVerilog Netlister Flows Conveniently
    By Andre Baguenier | 21 Sep 2020
    In this post, I will cover how HDL packages in Virtuoso can be set up for use in the AMS Designer flow.
    0 Comments
    Tags:
    SystemVerilog | Virtuoso-AMS | mixed signal design | HDL Package | AMS Designer
  • Lalit Mohan
    Start Your Engines: Pointers to Speed Up a Slow Mixed-Signal Simulation
    By Lalit Mohan | 14 Aug 2020
    There may be times when the mixed-signal verification engineers observe a slow analog mixed-signal (AMS) simulation. The complexity of design and inappropriate usage of simulator options may be the causes of this slowness.
    0 Comments
    Tags:
    mixed signal design | mixed-signal methodology | AMS Designer | analog behavioral models | mixed signal | wreal | real number models | SPICE | AMS Verification | vams | mixed-signal verification
  • Rick Sanborn
    Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL
    By Rick Sanborn | 20 Jul 2020
    The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process of SV UVM testbench reuse in the AMS UNL flow. Continue reading to know more.
    0 Comments
    Tags:
    SystemVerilog | AMS | uvm | Functional Verification | mixed signal methodology | AMS Designer | Mixed Signal Verification | Unified Netlister | SV-RNM | SVA | analog/mixed-signal | assertions | mixed signal | mixed-signal design | MDV | AMS Verification | mixed-signal verification | verification
  • Jommy
    Start Your Engines: The Blog-o-Meter Check
    By Jommy | 2 Jul 2020
    A summary of the blogs published in the Start Your Engines blog series.
    0 Comments
    Tags:
    CLIPS | mixed signal design | Functional Verification | AMS Designer | Unified Netlister | AMSD Flex Mode | mixed-signal verification
  • Lalit Mohan
    Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC Verification
    By Lalit Mohan | 18 Jun 2020
    Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel.
    0 Comments
    Tags:
    mixed signal design | mixed-signal methodology | AMS Designer | analog/mixed-signal | Virtuoso | axum | mixed signal | avum | mixed-signal verification
  • Rick Sanborn
    Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional Verification Flow
    By Rick Sanborn | 4 Jun 2020
    What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made possible with the latest Xcelium Mixed-Signal technologies from Cadence.
    0 Comments
    Tags:
    AMS | mixed signal design | AMS Designer | mixed signal solution | Verilog-AMS | analog | analog/mixed-signal | Virtuoso | RNM | wreal | AMS Verification | mixed-signal verification | verification
  • Qingyu Lin
    Start Your Engines: The Why and How of Generating Spectre Netlists for Analog Blocks Using UNL
    By Qingyu Lin | 21 May 2020
    Read to know about generating netlist in the Spectre native format using AMS UNL.
    0 Comments
    Tags:
    AMS Designer | Unified Netlister | analog/mixed-signal | mixed signal | AMS UNL | mixed-signal verification
  • Andre Baguenier
    Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!
    By Andre Baguenier | 30 Apr 2020
    This blog talks about how to enable the AMS Designer flex mode.
    0 Comments
    Tags:
    mixed signal design | AMS Designer | AMSD | AMSD Flex Mode | mixed-signal verification
  • Qingyu Lin
    Start Your Engines: AMSD Flex—Take your Pick!
    By Qingyu Lin | 16 Apr 2020
    Introduction to AMSD Flex mode and its benefits.
    0 Comments
    Tags:
    mixed signal design | AMS Designer | AMSD | AMSD Flex Mode | mixed-signal verification
  • msteam
    Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods
    By msteam | 21 Feb 2019
    Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These...
    0 Comments
    Tags:
    AMS | Virtuoso Schematic Editor | Low Power | virtuoso power manager | Virtuoso-AMS | mixed signal design | mixed signal solution | Virtuoso | low-power design | mixed signal | mixed-signal verification
  • msteam
    Take Advantage of Advancements in Real Number Modeling and Simulation
    By msteam | 26 Feb 2018
    Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor...
    0 Comments
    Tags:
    real number modeling | analog | Mixed-Signal | RNM | mixed-signal verification
  • msteam
    Integrating AMS IP in SoC Verification Just Got Easier
    By msteam | 6 Feb 2018
    Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations. But, what about...
    0 Comments
    Tags:
    AMS | mixed signal solution | Mixed-Signal | analog/mixed-signal | Virtuoso | mixed signal | Virtuoso environment | mixed-signal verification
  • msteam
    Automatically Reusing an SoC Testbench in AMS IP Verification
    By msteam | 4 Jan 2018
    The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently...
    0 Comments
    Tags:
    AMS | mixed signal design | mixed-signal methodology | mixed signal solution | analog | Mixed-Signal | analog/mixed-signal | Virtuoso environment | mixed-signal verification
  • TheLowRoad
    Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification
    By TheLowRoad | 10 Dec 2014
    Key Findings : There are a host of issues that arise in mixed-signal verification. As discussed in earlier blogs , the industry trends indicate that teams need to prepare themselves for a more mixed world. The good news is that these top five pitfalls are all avoidable. It’s always interesting to study the human condition. Watching the world through the lens of mixed-signal verification brings an interesting microcosm...
    1 Comments
    Tags:
    MS | uvm | Metric-Driven-Verification | Palladium | Mixed Signal Verification | Incisive | MDV-UVM-MS | Virtuoso | mixed signal | MDV
  • TheLowRoad
    Five Reasons I'm Excited About Mixed-Signal Verification in 2015
    By TheLowRoad | 3 Dec 2014
    Key Findings : Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it. As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the...
    0 Comments
    Tags:
    uvm | mixed signal design | Metric-Driven-Verification | Mixed Signal Verification | MDV-UVM-MS
  • TheLowRoad
    Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations)
    By TheLowRoad | 19 Nov 2014
    Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase. Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics...
    0 Comments
    Tags:
    Advantest | Palladium | Mixed Signal Verification | Emulation | mixed signal
  • TheLowRoad
    The Elephant in the Room: Mixed-Signal Models
    By TheLowRoad | 5 Nov 2014
    Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome. Without the magical models, the process breaks down for lack of performance, or holes in the chip verification. In the last installment of The Low Road , we were at...
    0 Comments
    Tags:
    metrics-driven methodology | real number modeling | uvm | CPF | RNM | UPF | mixed signal | MDV | verification
  • TheLowRoad
    It’s Late, But the Party is Just Getting Started
    By TheLowRoad | 30 Oct 2014
    Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed. The Cadence party for mixed-signal verification is the hottest ticket in town. With some important public events now behind us and more on the horizon, the agendas make it clear that there is mounting pain in the realm of verifying...
    0 Comments
    Tags:
    AMS | analog behavior | AMS-Designer | AMS Designer | analog behavioral models | analog/mixed-signal | AMS Verification
  • SumeetAggarwal
    How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your Desk?
    By SumeetAggarwal | 30 Apr 2014
    The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the system-on-chip (SoC) level. But today's mixed-signal designs have multiple...
    0 Comments
    Tags:
    real number modeling | AMS Designer | EDA training | SV-RNM | DMS | mixed signal | Schematic Model Generator | RAKs
  • DeveshJain
    Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL
    By DeveshJain | 10 Dec 2013
    Why is There a Need for Low Power Solutions? With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these electronic chips have also greatly increased. There has been a surge in the production of portable devices like mobile phones, laptops, tablets, and game boxes that support multiple applications and use various multimedia...
    0 Comments
    Tags:
    Low Power | mixed signal design | mixed-signal methodology | mixed signal solution | CPF | LVS | cdl | Schematics-XL | Mixed-Signal | analog/mixed-signal | Virtuoso | mixed signal
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