Mixed-Signal Design Blogs

In this post, I will cover how you can easily create an automatic configuration for a mixed-signal test bench.

In my previous post, I explained the three methods to convert an electrical signal to a real number. In this post, I will cover the methods to convert a real number signal to an electrical signal in your design.

This blog explains how to convert an electrical signal to a real number in your design.

This blog summaries the latest five blogs published in the Start Your Engines series.

The low-power format, CPF/UPF/IEEE1801, has been very popular in the digital simulation world for over ten years. Nowadays, it is also commonly used in the mixed-signal simulations.

In this post, I will explain how you could speed up your mixed-signal verification with the Spectre X simulator. I will also cover how Spectre X can be set up for use in the AMS Designer flows

In this post, I will cover how HDL packages in Virtuoso can be set up for use in the AMS Designer flow.

There may be times when the mixed-signal verification engineers observe a slow analog mixed-signal (AMS) simulation. The complexity of design and inappropriate usage of simulator options may be the causes of this slowness.

The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process of SV UVM testbench reuse in the AMS UNL flow. Continue reading to know more.

A summary of the blogs published in the Start Your Engines blog series.

Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel.

What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made possible with the latest Xcelium Mixed-Signal technologies from Cadence.

Read to know about generating netlist in the Spectre native format using AMS UNL.

This blog talks about how to enable the AMS Designer flex mode.

Introduction to AMSD Flex mode and its benefits.

Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These...

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor...

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations. But, what about...

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently...

Key Findings : There are a host of issues that arise in mixed-signal verification. As discussed in earlier blogs , the industry trends indicate that teams need to prepare themselves for a more mixed world. The good news is that these top five pitfalls are all avoidable. It’s always interesting to study the human condition. Watching the world through the lens of mixed-signal verification brings an interesting microcosm...

Key Findings : Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it. As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the...

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase. Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics...

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome. Without the magical models, the process breaks down for lack of performance, or holes in the chip verification. In the last installment of The Low Road , we were at...

Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed. The Cadence party for mixed-signal verification is the hottest ticket in town. With some important public events now behind us and more on the horizon, the agendas make it clear that there is mounting pain in the realm of verifying...

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the system-on-chip (SoC) level. But today's mixed-signal designs have multiple...