Custom IC Design

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Discussion

Practical limit to the number of elements in a vector port in VerilogA

Category: Custom IC Design

By Herge

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updated over 13 years ago by Andrew Beckett

1 replies • 13044 views
Discussion

How to use Tcl command to get expression value from a AMS simulation?

Category: Custom IC Design

By greatqs

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updated over 13 years ago by Andrew Beckett

6 replies • 17875 views
Discussion

2011 Models for TSMC RF90NM

Category: Custom IC Design

By JustinTaylor86

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updated over 13 years ago by Andrew Beckett

8 replies • 15031 views
Discussion

out-of-context probing

Category: Custom IC Design

By BradW

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updated over 13 years ago by Andrew Beckett

1 replies • 14164 views
Discussion

Virtuoso does not save certain nodes during transient simulation

Category: Custom IC Design

By Wonyoung

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updated over 13 years ago by Andrew Beckett

1 replies • 14805 views
Discussion

Custom Netlisting in ADE

Category: Custom IC Design

By GaneshShamnur

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updated over 13 years ago by Andrew Beckett

4 replies • 13345 views
Discussion

save data from outputs

Category: Custom IC Design

By surreyian

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updated over 13 years ago by Andrew Beckett

1 replies • 13451 views
Discussion

Undo pcell

Category: Custom IC Design

By RVERP

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updated over 13 years ago by RVERP

2 replies • 13645 views
Discussion

Parasitic devices/probes in the schematic --> How to fix the layout connectivity (flightlines) in VXL?

Category: Custom IC Design

By Wim Verhaegen

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updated over 13 years ago by Wim Verhaegen

4 replies • 2002 views
Discussion

how to activate/deactivate a component during a simulation

Category: Custom IC Design

By wighou

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updated over 13 years ago by Andrew Beckett

4 replies • 5799 views
Discussion

schematic and symbol pcells?

Category: Custom IC Design

By archive

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updated over 13 years ago by JaneCA

1 replies • 12987 views
Discussion

Generating LEF from layout view

Category: Custom IC Design

By BraveHeart

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updated over 13 years ago by Quek

1 replies • 17614 views
Discussion

is it possible to run LVS when the layout and schematic are in different library?

Category: Custom IC Design

By llobak

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updated over 13 years ago by narendra046

5 replies • 15211 views
Discussion

Assura 3.1.4 LVS failure

Category: Custom IC Design

By stefanobre

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updated over 13 years ago by stefanobre

5 replies • 14029 views
Discussion

multi-Core simulation with Ultrasim?

Category: Custom IC Design

By 01farhad10

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updated over 13 years ago by 01farhad10

4 replies • 14764 views

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