Functional Verification

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Discussion

IUS82s012: is this legal "for ( genvar g = 0; g < 4; ++g ) ..."?

Category: Functional Verification

By cubicle82

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updated over 16 years ago by cubicle82

2 replies • 1998 views
Discussion

Verilog Monitor to Check 'X' state of a Clock from the DUT.

Category: Functional Verification

By RaghavNS

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updated over 16 years ago by Mickey

2 replies • 8040 views
Discussion

AXI eVC: How to set a master agent to be read-only

Category: Functional Verification

By renvill

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updated over 16 years ago by Hilmar

1 replies • 13766 views
Discussion

Unresolved adapter error: ERR_DID_NOT_FIND_ADAPTER

Category: Functional Verification

By random

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updated over 16 years ago by random

1 replies • 14037 views
Discussion

How to probe a signal in verilog and VHDL.

Category: Functional Verification

By stanleyao

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updated over 16 years ago by stanleyao

4 replies • 21446 views
Discussion

ICCR coverage, ignore/cover parts of design

Category: Functional Verification

By sitanshu

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updated over 16 years ago by Mickey

1 replies • 1415 views
Discussion

merging code coverage from different design databases

Category: Functional Verification

By perezi

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updated over 16 years ago by nlin

1 replies • 20684 views
Discussion

Async signal assetions

Category: Functional Verification

By SVA1

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updated over 16 years ago by JoergM

1 replies • 13700 views
Discussion

gnu subdir is missing in IUS82/tools/SystemC/lib and .../lib/64bit

Category: Functional Verification

By NJSH

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updated over 16 years ago by NJSH

2 replies • 1143 views
Discussion

IUS82s12 is very slow !

Category: Functional Verification

By duckfly

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updated over 16 years ago by Adam Sherer

1 replies • 754 views
Discussion

Instance handeling during simulation

Category: Functional Verification

By WorkMan

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updated over 16 years ago by asedehi99

1 replies • 13645 views
Discussion

Disable Statements in NCVLOG

Category: Functional Verification

By anshman

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updated over 16 years ago by asedehi99

5 replies • 15442 views
Discussion

regardin "posedge clk iff rst == 0 " in system verilog

Category: Functional Verification

By onkarkk

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updated over 16 years ago by onkarkk

4 replies • 4297 views
Discussion

electromigration check

Category: Functional Verification

By depp

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updated over 16 years ago by tpylant

1 replies • 14264 views
Discussion

About Cadence Software tool

Category: Functional Verification

By SekarC

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updated over 16 years ago by tpylant

2 replies • 14605 views

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