Functional Verification

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Unresolved adater ERR_DID_NOT_FIND_ADAPTER

Category: Functional Verification

By random
•
updated over 17 years ago by random

2 replies • 15377 views
Discussion

Simulation Problem : resolving X of a un-initialized f/f whose output feedback to itself thru some logic

Category: Functional Verification

By iclcle
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updated over 17 years ago by StephenH

1 replies • 3821 views
Discussion

test to write and read registers with field order like packing.low

Category: Functional Verification

By mkyang
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updated over 17 years ago by StephenH

1 replies • 14639 views
Discussion

Verilog, System Verilog and SystemC

Category: Functional Verification

By jasonkee111
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updated over 17 years ago by mstellfox

3 replies • 20502 views
Discussion

generate of specman (vs) randomize of systemverilog

Category: Functional Verification

By onkarkk
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updated over 17 years ago by onkarkk

4 replies • 18109 views
Discussion

Simulation problem: unwanted zero-width glitch

Category: Functional Verification

By ridgemao
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updated over 17 years ago by Shalom B

3 replies • 23272 views
Discussion

FSM coverage and generate block

Category: Functional Verification

By karlsmartin
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updated over 17 years ago by StephenH

1 replies • 16218 views
Discussion

enum type dynamic array is giving an error with ius8.2-s006

Category: Functional Verification

By 123454321
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updated over 17 years ago by archive

1 replies • 14782 views
Discussion

empty/illegal list of parameters

Category: Functional Verification

By rashmikant
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updated over 17 years ago by archive

1 replies • 1692 views
Discussion

IUS82s012: is this legal "for ( genvar g = 0; g < 4; ++g ) ..."?

Category: Functional Verification

By cubicle82
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updated over 17 years ago by cubicle82

2 replies • 2650 views
Discussion

Verilog Monitor to Check 'X' state of a Clock from the DUT.

Category: Functional Verification

By RaghavNS
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updated over 17 years ago by Mickey

2 replies • 8558 views
Discussion

AXI eVC: How to set a master agent to be read-only

Category: Functional Verification

By renvill
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updated over 17 years ago by Hilmar

1 replies • 14950 views
Discussion

Unresolved adapter error: ERR_DID_NOT_FIND_ADAPTER

Category: Functional Verification

By random
•
updated over 17 years ago by random

1 replies • 15283 views
Discussion

How to probe a signal in verilog and VHDL.

Category: Functional Verification

By stanleyao
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updated over 17 years ago by stanleyao

4 replies • 23370 views
Discussion

ICCR coverage, ignore/cover parts of design

Category: Functional Verification

By sitanshu
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updated over 17 years ago by Mickey

1 replies • 1742 views

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