Functional Verification

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Discussion

generate of specman (vs) randomize of systemverilog

Category: Functional Verification

By onkarkk

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updated over 16 years ago by onkarkk

4 replies • 16918 views
Discussion

Simulation problem: unwanted zero-width glitch

Category: Functional Verification

By ridgemao

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updated over 16 years ago by Shalom B

3 replies • 21641 views
Discussion

FSM coverage and generate block

Category: Functional Verification

By karlsmartin

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updated over 16 years ago by StephenH

1 replies • 15323 views
Discussion

enum type dynamic array is giving an error with ius8.2-s006

Category: Functional Verification

By 123454321

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updated over 16 years ago by archive

1 replies • 14073 views
Discussion

empty/illegal list of parameters

Category: Functional Verification

By rashmikant

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updated over 16 years ago by archive

1 replies • 1376 views
Discussion

IUS82s012: is this legal "for ( genvar g = 0; g < 4; ++g ) ..."?

Category: Functional Verification

By cubicle82

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updated over 16 years ago by cubicle82

2 replies • 2182 views
Discussion

Verilog Monitor to Check 'X' state of a Clock from the DUT.

Category: Functional Verification

By RaghavNS

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updated over 16 years ago by Mickey

2 replies • 8155 views
Discussion

AXI eVC: How to set a master agent to be read-only

Category: Functional Verification

By renvill

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updated over 16 years ago by Hilmar

1 replies • 14205 views
Discussion

Unresolved adapter error: ERR_DID_NOT_FIND_ADAPTER

Category: Functional Verification

By random

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updated over 16 years ago by random

1 replies • 14480 views
Discussion

How to probe a signal in verilog and VHDL.

Category: Functional Verification

By stanleyao

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updated over 16 years ago by stanleyao

4 replies • 22055 views
Discussion

ICCR coverage, ignore/cover parts of design

Category: Functional Verification

By sitanshu

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updated over 16 years ago by Mickey

1 replies • 1496 views
Discussion

merging code coverage from different design databases

Category: Functional Verification

By perezi

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updated over 16 years ago by nlin

1 replies • 21415 views
Discussion

Async signal assetions

Category: Functional Verification

By SVA1

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updated over 16 years ago by JoergM

1 replies • 14113 views
Discussion

gnu subdir is missing in IUS82/tools/SystemC/lib and .../lib/64bit

Category: Functional Verification

By NJSH

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updated over 16 years ago by NJSH

2 replies • 1266 views
Discussion

IUS82s12 is very slow !

Category: Functional Verification

By duckfly

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updated over 16 years ago by Adam Sherer

1 replies • 814 views

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