• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      eDave
      eDave 70 Points
    • 3
      oldmouldy
      oldmouldy 55 Points
    • 4
      ShawnLogan
      ShawnLogan 50 Points
    • 5
      Elecguy
      Elecguy 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,734 Points
    • 2
      oldmouldy
      oldmouldy 13,695 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,710 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Not Answered

    3DXcanva does not suppress the unused pad on via

    Category: OrCAD X Presto PCB

    By gvellet

    •

    updated over 1 year ago by mahimag

    3 replies • 1637 views
  • Discussion

    vcvs has a wrong gain in montecarlo simulation

    Category: Custom IC Design

    By zuiying

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4914 views
  • Suggested Answer

    Unable to switch from SVN option to File System under Respiratory Server Type in OrCAD EDM

    Category: Allegro X Pulse & EDM

    By RohitRohan

    •

    updated over 1 year ago by RohitRohan

    2 replies • 2822 views
  • Discussion

    vias alignment

    Category: Allegro X PCB Editor

    By TiBo

    •

    updated over 1 year ago by zpofrp

    8 replies • 20894 views
  • Not Answered

    Find Routing problem (Route Vision) and quickly to fix these problems

    Category: Allegro X APD

    By zpofrp

    •

    updated over 1 year ago by zpofrp

    2 replies • 6063 views
  • Answered

    define via structure path

    Category: Allegro X PCB Editor

    By zpofrp

    •

    updated over 1 year ago by mahimag

    1 replies • 5788 views
  • Discussion

    Genus netlist generation (write_hdl) takes very long time

    Category: Digital Implementation

    By ACMTUG

    •

    started over 1 year ago

    0 replies • 5503 views
  • Discussion

    MOSFET dimension in schematic and LVS mismatch in TSMC 180nm I/O library

    Category: Custom IC Design

    By JadeCircuit

    •

    updated over 1 year ago by RobMan

    1 replies • 1618 views
  • Suggested Answer

    OrCad X standard vs OrCad X Professional

    Category: Allegro X PCB Editor

    By drobny

    •

    updated over 1 year ago by steve

    4 replies • 9861 views
  • Discussion

    rfTlineLib mlin non-physical behavior

    Category: Custom IC Design

    By TobyK

    •

    updated over 1 year ago by TobyK

    2 replies • 5093 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information