• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      eDave
      eDave 70 Points
    • 3
      AC20250829806
      AC20250829806 60 Points
    • 4
      oldmouldy
      oldmouldy 45 Points
    • 5
      ShawnLogan
      ShawnLogan 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,685 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,700 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Could anyone explain PSS+PAC simulation result of sampling circuit

    Category: Custom IC Design

    By fvoisin

    •

    updated over 1 year ago by fvoisin

    2 replies • 2071 views
  • Answered

    Access ORCAD command window using windows command prompt

    Category: Allegro X Capture CIS

    By Shanmugi

    •

    updated over 1 year ago by CadAP

    2 replies • 9474 views
  • Discussion

    Pegasus DRC Run fails

    Category: Custom IC Design

    By Saumeek

    •

    updated over 1 year ago by RobMan

    2 replies • 5594 views
  • Not Answered

    Change the name of a group of similar nets

    Category: Design Entry HDL

    By AGard

    •

    updated over 1 year ago by jc teyssier

    2 replies • 5067 views
  • Not Answered

    Matched group - Analyze choses wrong pin pair target

    Category: Allegro X PCB Editor

    By Fredda

    •

    updated over 1 year ago by jc teyssier

    7 replies • 3387 views
  • Not Answered

    Set up intersecting BOM variants in Capture CIS?

    Category: Allegro X Capture CIS

    By AB_1717461526428

    •

    updated over 1 year ago by Robert Finley

    1 replies • 3519 views
  • Discussion

    Floorplanning Problems in Mixed-Signal Design with Digital Block Pins Optimization

    Category: Mixed-Signal Design

    By Layouter5338

    •

    started over 1 year ago

    0 replies • 4101 views
  • Discussion

    ADE Schemetic simulation will not auto re-netlist Verilog-A Module

    Category: Custom IC Design

    By SimbaG

    •

    updated over 1 year ago by Frank Wiedmann

    3 replies • 4836 views
  • Answered

    Symbol classifications getting discarded in DFA PkgToPkg Spacing symbol browser - OrCad X

    Category: Allegro X PCB Editor

    By Jason T

    •

    updated over 1 year ago by mahimag

    6 replies • 3258 views
  • Not Answered

    Workspace and livebom possible problems with a corporate firewall

    Category: Allegro X Capture CIS

    By gvellet

    •

    updated over 1 year ago by gvellet

    3 replies • 3369 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information