• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Aurel B
      Aurel B 59 Points
    • 2
      AC20250829806
      AC20250829806 50 Points
    • 2
      SD20251126912
      SD20251126912 50 Points
    • 2
      SM202511279440
      SM202511279440 50 Points
    • 5
      excellon1
      excellon1 35 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,645 Points
    • 3
      eDave
      eDave 10,261 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,488 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Same Net Spacing: Shape to Shape

    Category: PCB Design

    By Fredda

    •

    updated over 5 years ago by Fredda

    1 replies • 14834 views
  • Discussion

    IDF Export to Solidworks (Holes not appearing)

    Category: PCB Design

    By JasonSn

    •

    started over 5 years ago

    0 replies • 13319 views
  • Discussion

    What is the range and type of number that spectre m factor can legally take?

    Category: Custom IC Design

    By LDIL

    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 13545 views
  • Discussion

    Portable Stmulus tool Perspec System Verifier

    Category: Functional Verification

    By BZKN

    •

    updated over 5 years ago by hannes

    1 replies • 15210 views
  • Discussion

    ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET

    Category: Functional Verification

    By zaratustra

    •

    updated over 5 years ago by zaratustra

    2 replies • 4078 views
  • Discussion

    Stability analysis Phase margin and loop gain

    Category: Custom IC Design

    By RakeshPRG

    •

    updated over 5 years ago by RakeshPRG

    4 replies • 28535 views
  • Discussion

    Sweep harmonic balance (hb) realibility (aging) simulation

    Category: RF Design

    By MAbyk

    •

    updated over 5 years ago by MAbyk

    2 replies • 17260 views
  • Discussion

    Pan & Zoom Very Slow in Allegro 17.4 - HF005 & Prior Versions - Windows 10

    Category: Allegro X PCB Editor

    By excellon1

    •

    updated over 5 years ago by RFinley

    10 replies • 9470 views
  • Discussion

    Choosing XF Magnitude of supply when measuring supply noise

    Category: Custom IC Design

    By david73

    •

    updated over 5 years ago by david73

    2 replies • 15499 views
  • Discussion

    Improved ACE/AXI backdoor access

    Category: Verification IP

    By RamkumarV

    •

    updated over 5 years ago by mocktail

    1 replies • 5207 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information