• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      KS202606109251
      KS202606109251 85 Points
    • 2
      AC202503109020
      AC202503109020 70 Points
    • 3
      HP20260601263
      HP20260601263 50 Points
    • 4
      FK202606088435
      FK202606088435 42 Points
    • 5
      RM202605273230
      RM202605273230 35 Points
  • Leaderboard

    • 1
      steve
      steve 17,869 Points
    • 2
      oldmouldy
      oldmouldy 13,830 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Not Answered

    TCL problem when get net name of pin in hierarchy design

    Category: Allegro X Capture CIS

    By LL202411014740

    •

    updated over 1 year ago by CadAP

    1 replies • 1923 views
  • Answered

    Trace loop in OrCad X

    Category: OrCAD X Presto PCB

    By MB202410295758

    •

    updated over 1 year ago by mahimag

    3 replies • 1948 views
  • Discussion

    Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors"

    Category: RF Design

    By Leandro Silva

    •

    updated over 1 year ago by Andrew Beckett

    2 replies • 3242 views
  • Suggested Answer

    AllegroX SPACING rule precedence

    Category: Allegro X PCB Editor

    By grax

    •

    updated over 1 year ago by techiecs

    1 replies • 4457 views
  • Discussion

    Display Resource Editor: Different Colors for Schematic and Layout Axis

    Category: Custom IC Design

    By sgcad

    •

    updated over 1 year ago by sgcad

    3 replies • 5796 views
  • Discussion

    How do you create a footprint symbol for a DIE that will be referenced in system capture schematic?

    Category: Allegro X APD

    By pattiwack

    •

    updated over 1 year ago by kanecharle

    1 replies • 14988 views
  • Discussion

    Flattening techLib VIA0/VIA1

    Category: Custom IC SKILL

    By Mallappa T

    •

    started over 1 year ago

    0 replies • 623 views
  • Answered

    Test point creation workflow recommendations?

    Category: Allegro X PCB Editor

    By JS202408156358

    •

    updated over 1 year ago by JS202408156358

    5 replies • 7281 views
  • Not Answered

    Find all the lock components in the schematic and unlock them

    Category: Allegro X Capture CIS

    By DW20241101210

    •

    updated over 1 year ago by DW20241101210

    2 replies • 2532 views
  • Discussion

    Quantus not running an returning error with no description

    Category: Custom IC Design

    By Awab

    •

    updated over 1 year ago by ConradJ

    1 replies • 5821 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information