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Breakfast Bytes: EDA in the Cloud: Astera Labs, AWS, Arm, and Cadence Report

Paul McLellan

Earlier this week I wrote a post covering the AWS presentation from HOT CHIPS about the Nitro project. Although the Nitro chips all contain Arm processors, that doesn't make them "Arm servers" in the sense that the processor running the application c...
- 4 Oct 2019
Analog/Custom Design: Virtuoso Video Diary: Multi-Technology Simulation—The Good has Changed for Better

Udit Rajput

This blog highlights the recent enhancements made to the Multi-Technology Simulation (MTS) feature.
- 3 Oct 2019
Breakfast Bytes: GLOBALFOUNDRIES Technology Conference 2019

Paul McLellan

This week was the GLOBALFOUNDRIES Technology Conference, GTC 2019, in Santa Clara. It was the 10th anniversary of GF, which was created on March 4, 2009. it is also almost exactly one year since what GF calls "the pivot", where they decided to abando...
- 3 Oct 2019
Breakfast Bytes: HOT CHIPS: The AWS Nitro Project

Paul McLellan

In 2016, Amazon acquired the Israeli company Annapurna Labs. Since they were in stealth mode, doing something to do with Arm processors, nobody really knew why. At the time, press reports called them "secretive chip maker Annapurna". Last year, at CD...
- 2 Oct 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA) for Electrical Engineers, Part 2

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett continues his introduction to finite element analysis (FEA) and the important role it can play in electronics deign. For a detailed explanation of the mathematics behind Finite Element Analysis, see this excellent video by Grasp Engineering: Practical Introduction and Basics of Finite Element Analysis

www.youtube.com/watch
- 1 Oct 2019
System, PCB, & Package Design : IC Packagers: Wrap Your Hands Around a Coil

Tyler

Coils are a design element that, if not exceedingly common, are showing up in more designs these days. They appear simple at first glance, but keeping a consistent air gap between each revolution of the spiral can involve a lot of mental arithmetic and picks in the design canvas. Here's how to do this with a few short clicks?
- 1 Oct 2019
Breakfast Bytes: The 2019 Kaufman Award Goes to Mary Jane Irwin

Paul McLellan

This year's Kaufman Award recipient is Dr. Mary Jane (Janie) Irwin of Pennsylvania State University. Dr. Irwin is the first woman to receive the Kaufman award, EDA's highest honor. As this morning's press release says: Dr. Irwin is ...
- 1 Oct 2019
Breakfast Bytes: TSMC OIP: Process Status

Paul McLellan

Last week was TSMC's Open Innovation Platform Innovation Forum (aka OIP). Dave Keller welcomed everyone and then introduced Cliff Hou who gave the update on everything technical. Here's what he said. Or rather, here's what I think he said...
- 30 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 29th September 2019

Paul McLellan

https://youtu.be/zU_y5sQBlGA Made at TSMC OIP Symposium (camera Tom Hackett) Monday: CDNLive Israel 2019: Celsius, the Dead Sea, Ramallah Tuesday: Running the Software for an Embedded System Wednesday: Embedded Development: Specialized Proc...
- 29 Sep 2019
System, PCB, & Package Design : BoardSurfers: PCB Electronics - Three Routing Challenges and Their Solutions

mrigashira

Routing is the core of a PCB. And, it's not an easy task. There are many challenges but, thankfully, there are solutions too. Here we list three common challenges and explain how to solve them.
- 27 Sep 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing—WSP-Based Tree Style Device Routing

Sravasti

This blog provides an overview of the last step of the Virtuoso Automated Device Placement and Routing solution. In this blog, I'll talk about the key benefits of the Automated Device-Level Routing functionality.
- 27 Sep 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之八 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：反向信道训练自动合规性检查有了详细的布局后互连以及IBIS-AMI模型的正确执行，您可以关注特定的、感兴趣的接口（本例中为PCI Express Gen 4）的合规性检查。每个接口都有自己的特定标准。在这种情况下，PCI Express确定了许多眼图相关的时域标准、无源互连通道的频域标准以及满足特定抖动容限范围的能力。单独评估这些标准可能会非常耗时，特别是，如果需要多次运行来扫描设计范围和多个通道模型的情形。用于通用串行链路标准的自动合规工具包通常会提...
- 27 Sep 2019
Breakfast Bytes: Building Neural Networks with High-Level Synthesis

Paul McLellan

Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus High-Level Synthesis. It was timed for the East Coast and for Europe, so I had to get up at 6:00am to attend, but since I'm still somewhat jet-lagged from gett...
- 27 Sep 2019
Breakfast Bytes: TSMC OIP: 6nm and 5nm

Paul McLellan

Today it is TSMC's Open Innovation Platform Ecosystem Forum, or OIP for short. This is one of two events each year at which TSMC presents much of the status of their technology, their fab construction, and production schedules. The other is the T...
- 26 Sep 2019
Breakfast Bytes: Embedded Development: Specialized Processing

Paul McLellan

Yesterday, in Running the Program for an Embedded System, I wrote about using emulation and FPGA prototyping to test and debug the software load for an SoC. But I didn't discuss where the software came from, just that somehow there was some obje...
- 25 Sep 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA) for Electrical Engineers, Part 1

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett begins a 2-part introduction to finite element analysis (FEA) by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. For a detailed explanation of the mathematics behind Finite Element Analysis, see this excellent video by Grasp Engineering: Practical Introduction and Basics of Finite Element…
- 24 Sep 2019
Breakfast Bytes: Running the Software for an Embedded System

Paul McLellan

A big challenge with developing a modern SoC is developing the software. Not so much the development itself, which is not very different from any other software development, but running and debugging the software. Waiting for the silicon to...
- 24 Sep 2019
System, PCB, & Package Design : IC Packagers: Finding Design Issues in SiP - Three Options for DRC Management During Sign Off

Tyler

Your design is complete. Yet, you have 20 DRC violations that need to be addressed (whether that means correcting the constraint required value, modifying objects, or waiving the DRC to sign off on it as okay). What’s the best way to go about r...
- 24 Sep 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help With Electromagnetic Analysis—Part I

Kabir

This blog is the first one in the multi-part series that aims at providing some in-depth details of electromagnetic analysis in the Virtuoso RF solution. To learn about a few tips and tricks on the process setup, read
- 23 Sep 2019
Breakfast Bytes: CDNLive Israel 2019: Celsius, the Dead Sea, Ramallah

Paul McLellan

The big announcement at CDNLive Israel was during Anirudh's keynote when he announced the second product in the system analysis space, Celsius. This is a thermal solver using both finite element analysis (for the solid parts) and computation...
- 23 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 22nd September 2019

Paul McLellan

https://youtu.be/6p94sN1fHFY Made at Tel Aviv seafront (camera Carey Guo) Monday: MLPerf: Benchmarking Machine Learning Tuesday: PCIe Gen 4: It's Official, We're Compliant Wednesday: Celsius: Thermal and Electrical Analysis Together...
- 21 Sep 2019
Breakfast Bytes: 500th Anniversary of Magellan's Voyage

Paul McLellan

Earlier this year, on July 20, we celebrated the 50th anniversary of the first landing on the moon. I wrote about it—well, mostly about the Apollo Guidance Computer—that day in my post The First Computer on the Moon. Increasingly, getting...
- 20 Sep 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing—Base Layer Fill Insertion

Sravasti

Welcome back to my next post in the Virtuoso Automated Device Placement and Routing blog series. At advanced node, after running the placer, there are a few additional requirements for base layers to be taken care of before the layout is routed and taken to completion. In this blog post, I’ll talk about how adding device fills helps meet these requirements. Read the post to know more.
- 19 Sep 2019
Academic Network: CDNLive Taiwan – Cadence User Conference 2019

Tracy Zhu

CDNLive Cadence User Conference is an opportunity for Cadence technology users, developers, industry experts, and academia to come together to network, share best practices on critical design and verification issues, and discover new t...
- 19 Sep 2019
The India Circuit: The Safety and Security of Autonomous Vehicle Systems

Madhavi Rao

At the recently-held CDNLive India 2019, Cadence’s annual user conference, we had a session by Cadence’s partners Green Hills Software. Green Hills Software is the worldwide leader in embedded safety and security. Cadence and Green Hills ...
- 19 Sep 2019

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