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Verification: Empowering Generation - Range Generated Fields (RGF)

teamspecman

Specman constraints solver process consists of a series of reductions and assignments. It reduces the range of the field value based on the constraints, and then assigns to it a random value from the reduced range. After assigning one field, the range of all connected fields is reduced accordingly, and the process continues until all fields are assigned.

A new feature added in Specman 18.03 – Range Generated Fields…
- 31 May 2018
Analog/Custom Design: Virtuosity: How to Run a Multi-Technology Simulation (MTS)?

Priyanka Dadwal

Are you looking for some hands-on experience with running multi-technology simulation in Virtuoso ADE Explorer and Virtuoso ADE Assembler? In today’s fast-shrinking technology, we often have situations where we need to design custom IC system-in-packages (SiP). But, here comes the challenge – how to design these ICs using different technologies in a single design environment and analyze their responses when there are…
- 31 May 2018
Breakfast Bytes: It'll be HOT on Sunday Evening at DAC

Paul McLellan

For several DACs now, Heart of Technology (HOT) has run a party on Monday night. This year there is a HOT party...but it is on Sunday night after the DAC welcome reception. Heart of Technology is a philanthropic organization started by Jim Hogan...
- 31 May 2018
Breakfast Bytes: 7 Ways to Get the Most out of DAC

Paul McLellan

DAC, the Design Automation Conference, is coming up. It's Sunday June 24th to Thursday June 28th in San Francisco. But in a slightly new location: Moscone West. The other halls, Moscone North and South, are halfway through a major reconstruction,...
- 30 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - The Advantages and Trade-offs of HBM2 and GDDR6

References4U

In this week’s Whiteboard Wednesday, Marc Greenberg discusses the advantages and trade-offs of two advanced memory interfaces: HBM2 and GDDR6, both targeted to the high-performance computing market.

www.youtube.com/watch
- 29 May 2018
Breakfast Bytes: If It's Tuesday This Must Be Belgium. My First Visit to imec

Paul McLellan

Outside of semiconductor, Belgium is famous for three things: beer, chocolate, and fries (which they eat with mayonnaise). Inside semiconductor, it is famous for imec. It's also famous for the 1969 movie If It's Tuesday, This Must Be Bel...
- 29 May 2018
Breakfast Bytes: Aren't All Crosswords Cryptic?

Paul McLellan

It's Memorial Day, so Breakfast Bytes is off today. Well, obviously not completely, since you're reading this. Pop quiz: what was Memorial Day called before it was called Memorial Day? Crosswords I have a hobby of sorts. I like to do cro...
- 28 May 2018
Analog/Custom Design: Virtuoso Video Diary: Bridging Virtuoso and Mixed-Signal Simulation Tools Using CLIPS

Vani V

Cadence has introduced Command-Line IP Selector (CLIPS) support to provide a bridge between Virtuoso—a UI-based, analog, and mixed-signal design environment—and other command-line, digital, and mixed-signal simulation tools and flows that use a text-based setup. CLIPS can be used to import an AMS IP into an existing digital-centric verification setup.
- 25 May 2018
Academic Network: Academic Network at VLSI-DAT Symposium in Taiwan 2018

Tracy Zhu

2018 was the second year Cadence Academic Network supported the VLSI-DAT Symposium in Hsinchu, Taiwan on April 16-18. We connected with around 500 attendees from local industry and academia. Taiwan is renowned as an IC design powerhouse. The VLS...
- 25 May 2018
Breakfast Bytes: GDPR Starts Today

Paul McLellan

You are probably subscribed to a number of email newsletters. No doubt you have been receiving emails saying that the system is changing the way that they are handling their mailing lists and that if you want to continue to receive the emails, then ...
- 25 May 2018
Breakfast Bytes: Embedded Vision: Seeing 20,000X Improvement

Paul McLellan

This week it is the Embedded Vision Summit in Santa Clara. Over the last few years, vision has gone from something esoteric to a mainstream part of many systems, with ADAS in automobiles, smart security cameras that analyze the video stream, dr...
- 24 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 28th to June 1st 2018

Paul McLellan

https://youtu.be/UEAZjA-_xrE Coming from Embedded Vision Summit (camera Sean) Monday: Memorial Day off-topic Tuesday: If It's Tuesday This Must Be Belgium Wednesday: 7 Ways to Get the Most out of DAC Thursday: It's HOT on DAC Sun...
- 23 May 2018
Breakfast Bytes: MEMS Design Competition: The Envelope Please...

Paul McLellan

The Cadence Academic Network sponsored a MEMS design contest over the last couple of years. At CDNLive EMEA 2018, the winners were announced. The idea was to encourage groups to design using a mixture of the Cadence analog/mixed-signal design tools, ...
- 23 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - The Truth about Designing for Automotive Functional Safety

References4U

In this week’s Whiteboard Wednesday, Tom Hackett challenges conventional wisdom and concludes that achieving functional safety means going beyond the letter of the law of ISO 26262 to embrace the spirit of a functional safety culture.

www.youtube.com/watch
- 22 May 2018
Breakfast Bytes: Accelerating AI: ...Present and Future

Paul McLellan

Yesterday I wrote about the first part of Krste Asanović's presentation Accelerating AI: Past, Present, and Future. Although yesterday's post only covered the past. Today, it's time for the present and future. Graphics Processing Units GP...
- 22 May 2018
Breakfast Bytes: Accelerating AI: Past...

Paul McLellan

SiFive does a quarterly series of tech talks, not necessarily directly to do with SiFive or even RISC-V. For example, last quarter it was Paul Kocher (and if you don't know that name, you need to go and read my post about that talk Paul Koc...
- 21 May 2018
Breakfast Bytes: CGTN China 24 Interview

Paul McLellan

https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week, being interviewed about the Chinese Semiconductor Industry. www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email.
- 18 May 2018
Analog/Custom Design: Virtuosity: What's New in Run Plan – Part II

Yagya Mishra

The Run Plan assistant in Virtuoso ADE Assembler has proved to be one of the most popular features. It provides the capability to create multiple variations of the setup within a single session, each of these runs has their own setup details that override the settings in the active setup. Simulations can be run for all the runs defined in the run plan with a single click. If there are no dependencies, the results are…
- 18 May 2018
Breakfast Bytes: Achronix Grew 700% Last Year...eFPGA is a Thing

Paul McLellan

I don't normally write about the FPGA market. There are three reasons for this. First, Cadence doesn't participate in the market for FPGA tools (for FPGA users. I'm pretty sure the arrays themselves are almost all designed on Virtuos...
- 18 May 2018
Breakfast Bytes: CDNDrive: ISO 26262...Chapter 11

Paul McLellan

At CDNLive EMEA Robert Schweiger laid out his perspective on the automotive market. At April’s CDNLive Silicon Valley too, but as you might guess from his name, Germany is his home. Sanjay Lall, the head of Cadence EMEA, had told me the day bef...
- 17 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - An Introduction to Compute In-Memory

References4U

In this week’s Whiteboard Wednesday, Marc Greenberg introduces the concept of “Compute In-Memory” - a hot topic which promises to greatly improve the performance of memory transactions while reducing energy. However, there are alternate approaches that can accomplish the same goals with today’s technology. This video explores the approach and alternatives.

https://youtu.be/61J2R42yAzQ
- 16 May 2018
Breakfast Bytes: TSMC: Mobile, HPC, IoT, Automotive...and Packaging

Paul McLellan

This is the third post about the TSMC Technology Symposium that was held on May 1st. The first two are TSMC Technology Symposium 2018 and TSMC's Fab Plans and More. In the afternoon, there were four presentations: Doug Yu on Advanced Packag...
- 16 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 21st to 25th 2018

Paul McLellan

https://youtu.be/AmlYRYzIHtY Coming from my office (camera Sean, guest star Alexa) Monday: Accelerating AI: Past... Tuesday: Accelerating AI: ...Present, and Future Wednesday: MEMS Design Competition. The Envelope Please Thursday: The...
- 15 May 2018
The India Circuit: Inspiration, Networking and Food For Thought

Chandrika Durbha

Recently I had the opportunity to attend the Society of Women Engineers (SWE) Conference in Pune, India. But before I get into talking about the Conference, I want to tell you about an incident that got me thinking. While in Pune, I visited my ...
- 15 May 2018
Breakfast Bytes: CDNLive: Testing Times in Munich

Paul McLellan

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning, or parallel simulation get all the attention. But a chip doesn't only have to be manufactured, it also has to be tested. At CDNLive EMEA I met Erik Jan Marinissen o...
- 15 May 2018

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