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Breakfast Bytes: Superhuman Photonic Design

Paul McLellan

I recently came across an article titled Generative Design Could Radically Transform the Look of Our World. No, the article wasn't about semiconductor design... at least not yet. It was about architecture. And chairs. For example, the image ...
- 11 Apr 2019
Breakfast Bytes: TI's Experience Taping out with Pegasus

Paul McLellan

At the recent CDNLive Silicon Valley, Kyle Peavy of Texas Instruments (TI) presented Cadence Pegasus Physical Verification: A Customer Tapeout Experience, along with Cadence's Digo (Dibyendu) Goswami. Obviously, just based on the title, TI taped...
- 10 Apr 2019
Analog/Custom Design: Virtuoso Video Diary: Tune In to the MPT Video Channel

KomalJohar

Tune In to the MPT Video Channel to check out a wide range of features easily accessible through the MPT toolbar.
- 9 Apr 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill

References4U

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion, usually at the signoff stage, is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage…
- 9 Apr 2019
Breakfast Bytes: Barefoot in a CloudBurst: Tempus on 2000+ CPUs

Paul McLellan

Barefoot Networks gave a couple of presentations at the recent CDNLive Silicon Valley. Both presentations were about the latest member of their Tofino family of ASICs. This networking chip has a throughput of 12.8Tbps and is fully programmable. It ha...
- 9 Apr 2019
Breakfast Bytes: Driving Dangerously

Paul McLellan

I've written a few times before about the fragility of neural networks, for example in last year's post Fooling Neural Networks. There is an unstated assumption underlying the training of neural networks that the environment is benign, a...
- 8 Apr 2019
Breakfast Bytes: Sunday Brunch Video for 7th April 2019

Paul McLellan

https://youtu.be/DUu3M30lilE Made at CDNLive Silicon Valley (camera Sean) Monday: CloudBurst: The Best of Both Worlds Tuesday: Bringing Clarity to System Analysis Wednesday: Geoff Hinton, Yann LeCun, and Yoshua Bengio Win 2019 Turing Award Thursday: ...
- 7 Apr 2019
PCB、IC封装：设计与仿真分析: Chiplets——重新定义系统设计

Sigrity

当下，电子行业经历着系统设计的新范式转变：传统的单片SoC电子系统设计思路正逐渐转变为使用chiplets（即“小芯片”）和高级封装技术的多芯片设计方法。这种逆转思维为系统设计开启了一个新的时代。什么是chiplets和基于chiplets的系统？ Chiplets的概念其实已存在了几年，随着高级互连和封装技术的日趋成熟，人们对它的关注越来越大。Chiplets是已知的良好芯片，通常具有单一特定功能，并且包含具有小型微缓冲器的封装器、级别转换能力、启用测试，以及利用诸...
- 5 Apr 2019
The India Circuit: Simple Things You Can Do To Get Ahead In The Workplace

Madhavi Rao

Recently we were lucky to have two of the women vice presidents at Cadence – Karna Nisewaner from the Legal team and Alessandra Costa who leads the Field Engineering team in North America – visit India and have interaction sessions with o...
- 5 Apr 2019
Breakfast Bytes: RSA: Public Interest Technologists

Paul McLellan

Yesterday, I wrote about the first half of Bruce Schneier's keynote at the recent RSA Conference in San Francisco. Today, the second half, and the audience Q&A. If you work in security in any way, or just have some interest in the area, you o...
- 5 Apr 2019
Analog/Custom Design: Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

NamrataM

How about checking your designs for electromigration (EM) compliance before creating layouts? Why not? Read further to know more ...
- 4 Apr 2019
Breakfast Bytes: RSA: Bruce Schneier

Paul McLellan

I have been following Bruce Schneier for a long time. He literally wrote the book on cryptographic algorithms, Applied Cryptography, in two editions, both of which I own. He has run an email newsletter, Crypto-Gram, since 1998 (subscribe). He has a b...
- 4 Apr 2019
Academic Network: Best Paper Award at LATS2019 for Zhan Gao

Anton Klotz

The IEEE Latin-American Test Symposium (LATS) is an annual forum attended by professionals and technologists from all over the world. It is an event where various aspects of system, board, and component testing and fault-tolerance are presented...
- 3 Apr 2019
System, PCB, & Package Design : BoardSurfers: Validating Your Shapes

Tyler

Your design is near completion. Except that you’ve got an area of your plane shape that stubbornly refuses to fill, and you don’t know why. Understanding the rules involved and the tools available to help you figure out – and make changes, if needed, to get the result you want – is critical to make sure you aren’t wasting valuable design cycles.

Thankfully, the Cadence® Allegro® platform…
- 3 Apr 2019
Breakfast Bytes: Geoff Hinton, Yann LeCun, and Yoshua Bengio Win 2019 Turing Award

Paul McLellan

This year's Alan Turing Award goes to Geoff Hinton, Yann LeCun, and Yoshua Bengio. According to the New York Times, they are the "Godfathers of Deep Learning", presumably in the non-mafia sense ("nice neural network you've got ...
- 3 Apr 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - When it Comes to Cloud-Based Design, One Size does Not Fit All

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett describes how different types of companies possess different combinations of 3 key assets needed for successful cloud-based electronics design. Since their assets are different, the solutions they need for cloud-based design are also different.

https://youtu.be/RVSlR8ZPRuo
- 2 Apr 2019
Breakfast Bytes: Bringing Clarity to System Analysis

Paul McLellan

Today, at CDNLive Silicon Valley, Lip-Bu Tan, Cadence's CEO, announced the Clarity 3D Solver during his keynote. This is the first product in Cadence’s system analysis effort, break-through EM simulation technology that delivers 10X performance...
- 2 Apr 2019
Verification: Cadence Announces Continued Partnership With Northrop Grumman

XTeam

On March 28th, 2019, Cadence Design Systems announced an expanded collaboration with Northrop Grumman centering on advanced-node SoC projects. Cadence’s cutting-edge verification tools are combining with Northrup Grumman’s expertise to deliver high performance ASICs more efficiently. Northrop Grumman will be using the full flow of Cadence ASIC development tools including verification, digital synthesis and…
- 1 Apr 2019
Verification: Cadence Leads the Pack: The First VIP for USB4 is Here!

XTeam

On March 14th, Cadence announced the release of the industry’s first USB4-supporting Verification IP! The Cadence VIP for USB4 allows engineers to design and create cutting-edge SoC designs compliant with the current standards that are completely functionally verified and require less time.

“Support from [USB Implementers Forum] members like Cadence helps reduce the barriers to adoption of new USB protocols and…
- 1 Apr 2019
Breakfast Bytes: CloudBurst: The Best of Both Worlds

Paul McLellan

I think if you were starting a new semiconductor company, you would go straight for a cloud-based solution and not bother with the cost and complexity of building up your own datacenter, and the black-belt IT department needed to install an...
- 1 Apr 2019
Breakfast Bytes: Sunday Brunch Video for 31st March 2019

Paul McLellan

https://youtu.be/2_zmjd8wM0c Made on my balcony (camera Carey Guo) Monday: AI Index Tuesday: 8 Ways to Get the Most out of CDNLive Silicon Valley Wednesday: The Ladybird Book of Quantum Mechanics Thursday: Scaling EDA in the Cloud Friday: Twenty Year...
- 31 Mar 2019
PCB、IC封装：设计与仿真分析: Cadence专家培训计划正式启动

SDA China

感谢您对Cadence的关注与支持，我们的微信服务号“Cadence楷登PCB及封装资源中心”已正式上线。我们遵循Cadence所倡导的 “系统设计实现” 策略助力工程师们优化设计、缩短开发周期、打造行业领先产品。我们在传递最新行业动向、观点要闻的同时更加专注于与大家分享PCB及封装设计、SI/PI、多物理场仿真分析等领域的技术干货与培训资源。在这里，大家将获得：最新、最详细的教学视频、白皮书、会议讲义、产品说明书等技术资料的查看与下载；...
- 29 Mar 2019
定制IC芯片设计 : Virtuosity: 交互辅助布线命令的快捷键使用指南

Parula

摘要：对于使用快捷键（bindkeys）的好处，相信您在日常工作中已深有体会。那么，为了帮助用户获得更好的体验，本文介绍了Virtuoso 交互辅助布线相关的常用快捷键，赶快阅读，获取更多信息！
- 29 Mar 2019
Breakfast Bytes: Twenty Years in the Matrix

Paul McLellan

It is hard to believe, but Sunday will be the 20th anniversary of The Matrix. It was released on 31st March 1999. I'm going to assume you've seen it. At this point, if you haven't, it's probably somewhat spoiled for you anyw...
- 29 Mar 2019
System, PCB, & Package Design : BoardSurfers: Dynamic Shape Voiding – Getting the Most Out of the Tool

Tyler

Dynamic shapes; whether used on a negative or positive artwork layer, for power, ground, or signal; are the next most common element of a design after components and routing. The importance of using them effectively, then, can be the difference between a design that is DRC-free, ready on time, and easy to update for ECOs (Engineering Change Orders) and one that you seem to struggle with on a daily basis trying to force…
- 28 Mar 2019

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