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Latest Blog Posts

  • Breakfast Bytes: The Birthplace of Silicon Valley: 391 South San Antonio Road

    Paul McLellan
    Paul McLellan
    The birthplace of Silicon Valley really does have an address, 391 South San Antonio Road. In fact, it has two addresses, 844 Charleston Road as well. But the San Antonio Road one is earlier by a couple of years. There will be a plaque unveiling there...
    • 13 Aug 2018
  • Breakfast Bytes: Deep Learning and the Cloud

    Paul McLellan
    Paul McLellan
    It is an exaggeration to say that deep learning requires the cloud, but the standard way to do the training part of deep learning has become the cloud, especially servers equipped with NVIDIA GPUs. EDA is involved in deep learning in several differen...
    • 10 Aug 2018
  • Breakfast Bytes: What's For Breakfast? Video Preview August 13th to 17th 2018

    Paul McLellan
    Paul McLellan
    https://youtu.be/H03oGGaUfQo Coming from Stevens Creek Mini (camera Sean) Monday: 391 South San Antonio Road Tuesday: CDNDrive: Cadence Automotive Solutions Wednesday: 7nm Is a Dress Rehearsal for 5nm Thursday: The Birthplac...
    • 10 Aug 2018
  • Breakfast Bytes: Breakfast Buffet for July

    Paul McLellan
    Paul McLellan
    https://youtu.be/JQz3cseZcZc The three highlighted posts for July were: CDNLive Japan: 対応ポートフォリオ Liberate Trio: Characterization Suite in the Cloud Cadence Is MAGESTIC Sign up for Sunday Brunch, the weekly Breakfast Bytes email.
    • 9 Aug 2018
  • System, PCB, & Package Design : EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 3 of 4)

    Sigrity
    Sigrity
    In part 2 of this blog series we looked at the three different modes of heat transfer and related them to equivalent thermal resistances.  In this blog, we’ll use the concept of thermal resistors to develop a thermal equivalent network of...
    • 9 Aug 2018
  • Breakfast Bytes: CHIPs in the Cadence Cafeteria

    Paul McLellan
    Paul McLellan
    Last week it was the Annual San Jose Intern Showcase, in which the San Jose based interns all set up posters across the back of the building 10 cafeteria for a couple of hours. How Many Interns Are There? I go to this event, talk to some interns, and...
    • 9 Aug 2018
  • PCB、IC封装:设计与仿真分析: 升级到Allegro17.2-2016的10大理由

    TeamAllegro
    TeamAllegro
    Cadence Allegro 17.2-2016是过去十年中发布的最大版本,于2016年4月下旬发布。由于17.2-2016版本包含数据库更改,通常会出现在零版本中,很多人想知道何时是升级的最佳时间。 如下列出了升级到Allegro 17.2-2016版本的十大理由,以便您更好地理解每一项的价值。 本文将帮助您学会Allegro 17.2-2016版本中的这些新功能,并从中受益。 在这一期文章发布之后,我们将针对每一项作更详细的介绍。 1.先进的柔性和刚柔结合板设计支持 &ndash...
    • 8 Aug 2018
  • Breakfast Bytes: CDNLive Japan: The Fourth Industrial Revolution and the Third Dimension

    Paul McLellan
    Paul McLellan
    At CDNLive Japan, Tom Beckley gave the keynote Enabling the Fourth Industrial Revolution (Industry 4.0). At one point he announced Sigrity 2018, the latest version of the Sigrity power and signal integrity analysis tool, now merging in a lot of mecha...
    • 8 Aug 2018
  • Analog/Custom Design: Virtuoso: The Next Overture – DRD Launches New Interface

    Pallabi R
    Pallabi R
    If you’ve been anywhere near the Cadence news buzz the last couple of months, you must have heard about the DRD relaunch. Let’s have a closer look at what the new DRD brings to you.
    • 7 Aug 2018
  • Breakfast Bytes: Lung Chu on Semiconductor in China

    Paul McLellan
    Paul McLellan
    I talked Friday about the Chinese American Semiconductor Professionals Association (CASPA) summer event in my post CASPA: Innovation with Chinese Characters. Ajit Manocha, the CEO of SEMI, gave a short opening welcome and introduced Lung Chu, wh...
    • 7 Aug 2018
  • The India Circuit: Of HD Maps, Road Safety And Deep Networks

    Madhavi Rao
    Madhavi Rao
    Cadence India hosted a first-of-its-kind seminar recently that talked about the need artificial intelligence (AI) processing will have for high speed connectivity. The central theme was that the next era of AI processing mandates hyper-connectivity t...
    • 7 Aug 2018
  • PCB、IC封装:设计与仿真分析: 警惕发热!——热模型交换

    Sigrity
    Sigrity
    如今,工程师们面临着复杂且快速的设计变更,需要运用多个设计工具才能协同完成。 MCAD和ECAD的设计系统由于采用其中性文件格式(如SAT、IGES、IDF等),已经很好地解决了这个问题。然而,在一个设计的关键领域——即热仿真领域,中性文件概念尚未采及。这导致了计算流体动力学(CFD)分析软件中缺乏标准化的文件格式,从而使得热工程师们多年来备受煎熬。标准化的缺乏是造成整个供应链存在严重低效率瓶颈的罪魁祸首,并且转换错误及其它错误更会导致模型精准度出现问题,从而大大增加原...
    • 6 Aug 2018
  • Breakfast Bytes: Simulation in the Cloud

    Paul McLellan
    Paul McLellan
    Yes, despite the blue skies, Fridays are still cloudy. And, yes, this isn't Friday. Due to a migraine out of the blue, Friday got postponed to Monday. When I was at CDNLive Japan, Craig Johnson ran a demonstration of using Orchestrator to launch ...
    • 6 Aug 2018
  • PCB、IC封装:设计与仿真分析: 封装/ PCB系统的热分析:挑战及对策

    Sigrity
    Sigrity
    如今越来越多的封装/ PCB系统设计需要进行热分析。 功耗是封装/ PCB系统设计中的关键问题,需要仔细考虑热和电两个领域的问题。 为了更好地理解热分析,我们以固体中的热传导为例,并利用两个领域的对偶性。 图1和表1描述了电域与热域之间的基本关系。 图1. 电域与热域之间的基本关系(点击查看大图) 表1. 电域与热域之间的基本关系(点击查看大图) 电域与热域之间存在一些差异,比如: 在电域,电流被限制在特定电路元件内流动,但在热域中,热流通过三种热传导机制(传导、对流和辐射)在三维空间从...
    • 3 Aug 2018
  • PCB、IC封装:设计与仿真分析: 欢迎访问Cadence公司PCB、IC封装:设计与仿真分析博客

    SDA China
    SDA China
    我们将与您分享有关PCB和IC封装设计与仿真分析的最新资讯; 在这里,您可以纵观科技前沿、行业动态与展会讯息; 在这里,您可以获得如下专题的详细信息: • 最新产品/功能发布 • 视频教程 • 行业洞察 • 用户体验 • 研讨会/行业展会议程及资料下载 这里凝结着工程师们的智慧与成果,我们与您真诚分享。 最新技术资讯详情请访问: PCB设计 IC封装设计 PCB与IC封装仿真分析 欢迎订阅“PCB、IC封装:设计与仿真分...
    • 3 Aug 2018
  • Breakfast Bytes: CASPA: Innovation with Chinese Characteristics

    Paul McLellan
    Paul McLellan
    A couple of times per year, the Chinese American Semiconductor Professionals Association (CASPA) holds a meeting. Despite the name, you don't have to be Chinese to go, and all the presentations are in English (although sometimes there are slides with...
    • 3 Aug 2018
  • Breakfast Bytes: What's For Breakfast? Video Preview August 7th to 11th 2018

    Paul McLellan
    Paul McLellan
    https://youtu.be/xPVzOfBHGlM Coming from Cadence Intern Showcase (camera Sean) Monday: CASPA: Innovation with Chinese Characteristics Tuesday: Lung Chu on Semiconductor in China Wednesday: The Fourth Industrial Revolution and the...
    • 2 Aug 2018
  • Digital Design: QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

    SeanDart
    SeanDart

    Whenever we talk to potential customers about Stratus HLS, we usually mention that many users get better quality of results (QoR) with a Stratus HLS flow than they did simply writing RTL by hand. Often, we are greeted with looks of skepticism or downright disbelief. We are usually asked the honest question:

    Can Stratus HLS really achieve better QoR than we can get using traditional RTL coding?

    I assure you that it can…

    • 2 Aug 2018
  • Analog/Custom Design: Virtuoso Video Diary: Single Schematic Flow in Virtuoso System Design Platform

    deeptig
    deeptig
    The Single Schematic Flow in Virtuoso System Design Platform simplifies the product usage. It allows you to generate a hierarchical schematic that can be used for simulations as well as for driving the layout of the package.
    • 2 Aug 2018
  • Breakfast Bytes: ITF: CFETs and New Interconnect

    Paul McLellan
    Paul McLellan
    At the imec technology forum (ITF) held the day before SEMICON West opened, two of the presentations were about future technologies, one focused on the FEOL, front-end-of-line, meaning the transistors. The other was focused on BEOL, back-end-of-...
    • 2 Aug 2018
  • Breakfast Bytes: How to Pitch a Journalist

    Paul McLellan
    Paul McLellan
    In the early part of my career, I was an engineer or an engineering manager. Then, I moved into operational management and marketing, which meant I spent a fair bit of my time talking to journalists. Without really planning it, when I found myse...
    • 1 Aug 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the evolving von Neumann computer architecture and the adaptations driven by recent cloud computing challenges. The effort to overcome these challenges has led to the development of a new industry standard called the Cache Coherent Interconnect for Accelerators (CCIX).

    https://youtu.be/D8pzVq4uJ-E

    • 31 Jul 2018
  • Verification: Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meetings

    XTeam
    XTeam

    We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it was a virtual meeting—but those never really feel the same in person, do they? Attending a virtual meeting can feel cold and impersonal, especially since you can barely see everyone else. Everyone is there except you—and even then, saying you’re “there” is a bit of a stretch.

    Nowadays, though, there…

    • 31 Jul 2018
  • Breakfast Bytes: GLOBALFOUNDRIES' CTO State-of-the-Roadmaps

    Paul McLellan
    Paul McLellan
    At SEMICON I got to sit down with Gary Patton, the CTO of GlobalFoundries. They have a dual roadmap, with both 14nm FinFET (licensed from Samsung) going to 7nm (internally developed), and with the other track being FD-SOI (licensed originally from ST...
    • 31 Jul 2018
  • Breakfast Bytes: Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness

    Paul McLellan
    Paul McLellan
    At SEMICON West, Dave Patterson (center) sat down for an interview with author John Markoff (left). Also on stage was Mark Hill (right), who is a professor at the University of Wisconsin, but he was one of Dave's early students at UC Berkeley. D...
    • 30 Jul 2018
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