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Life at Cadence: Computational Software: Foundation for an Optimal Digital Design and Signoff Full Flow

Corporate

Cadence has started to use the term, “computational software,” to collectively refer to a superset of algorithms and technologies powering electronic design automation (EDA) tools. Providing the most powerful computational software for ED...
- 1 Nov 2022
Breakfast Bytes: TSMC OIP: FINFLEX, Analog Migration, mmWave, and Awards

Paul McLellan

Last week it was "OIP," TSMC's Open Innovation Platform Ecosystem Forum. My day consisted of attending the keynotes, where we were not allowed to take photos, followed by a press event (where TSMC gave us the slides!), followed by the T...
- 1 Nov 2022
Computational Fluid Dynamics: Cadence Welcomes Cascade Technologies

John Chawner

Cadence welcomes Cascade Technologies, an innovator in the field of computational fluid dynamics (CFD). Staffed by experts, many with backgrounds originating at Stanford University (the Center for Turbulence Research and the Advanced Simulation ...
- 1 Nov 2022
Verification: PCIe Lane Margining - What changed from Gen4 to Gen6?

mrana

With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s, which doubles to 32GHz which further causes frequency dependent loss increased to 70dB, PAM4 was introduced.

Use of PAM4 signaling address the issues related to integrity, channel loss and backward compatibility but increased…
- 31 Oct 2022
カスタムIC／ミックスシグナル: Start Your Engines: AMS Designerのテストケースをクローンして、どこでも再実行可能

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。こんにちは！この記事...
- 31 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

Happy Monday and welcome to this extra spooky edition [obligatory Halloween reference] of Last Week at Fidelity CFD. From the Blogs On-Demand Webinar - Reduce Ship Fuel Emissions and Costs Through CFD Optimization Ship designs are becoming mor...
- 31 Oct 2022
Breakfast Bytes: October Update: AWS, Knuth, CHIPS

Paul McLellan

The last Friday of the month is my day for an update post, including updates to earlier posts, and stories that do not justify their own post. But Friday was a Cadence Global Recharge Day and so I pushed it out to today, the last day of the month. AW...
- 31 Oct 2022
Computational Fluid Dynamics: 8 Less-Explored Powerful Commands on Fidelity Pointwise

Veena Parthan

The essential steps in mesh generation are the same, no matter what type of mesh you generate. 80% of your mesh is generated using only 20% of the software's functionality leaving much of the mesh generator's functionality unexplored. This blog article enumerates 8 powerful commands on Fidelity Pointwise that can speed up the entire process, including meshing.
- 31 Oct 2022
Analog/Custom Design: Spectre Tech Tips: How to Migrate to Spectre X?

Moustafa Moham

Are you still using Spectre APS and you want to migrate to Spectre X? If yes, this post will guide you how to move to Spectre X and will also answer your questions about the preset modes mapping, postlayout circuits, and the impact of Spectre APS fine-tuned netlist options on Spectre X performance.
- 31 Oct 2022
Digital Design: Training Insights – Webinar – Transforming your Timing Signoff Experience with Tempus SSV221: Registrations Open

sakshin

This webinar encourages you to learn and apply the latest innovations in the Cadence®︎ Tempus Timing Solution SSV221 Release.
- 30 Oct 2022
Verification: CXL Enumeration: How Are Devices Discovered in System Fabric?

Sangeeta Soni

PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery. CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex integrated endpoints (RCiEP) during software enumeration process. Notably, there is a difference between the discovery of CXL 1.1 versus the CXL 2.0 device. Hence, the configuration space for CXL1.1 and CXL 2.0 varies. In this…
- 27 Oct 2022
Life at Cadence: Making Sustainable Data Center Design Possible with Digital Twins

Nimish Modi

Cadence has expanded into the realms of systems design and computational fluid dynamics (CFD). Cadence’s acquisition of Future Facilities, a pioneer in the data center digital twin space, expands our CFD and thermal analysis portfolio and extends it to data centers. In addition to electronics cooling analysis, Future Facilities’ innovative solutions enable customers such as Thésée DataCenter, Digital Realty, and Equinix…
- 27 Oct 2022
Life at Cadence: CalSol Is Paving the Way for Solar Vehicles

Corporate

CalSol is on a mission to design, build, test, and race the world’s fastest and most solar-efficient vehicles. A team of undergraduate students from the University of California, Berkeley, CalSol was founded in 1990, and since then, they have b...
- 27 Oct 2022
Breakfast Bytes: PACMAN and Using Jasper for Security Verification

Paul McLellan

At the recent Jasper User Group meeting, there were a couple of presentations on using the Jasper apps for security verification, specifically Jasper SPV (for Security Path Verification): HW Security Path Validation Using Formal Methods: Intel ...
- 27 Oct 2022
RF /マイクロ波設計: μWaveRiders:Cadence AWR Design Environment V22.1 ソフトウェアのリリースをハイライト

RF Design Japan

The Cadence AWR Design Environment V22.1 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.
- 26 Oct 2022
Breakfast Bytes: TSMC OIP: N3E/N4P, 3DFabric, Analog Migration

Paul McLellan

Today, it ia TSMC's OIP, the Open Innovation Platform Ecosystem Forum. I will write about some of what was said there soon. But in the meantime, as usual, Cadence has made several announcements jointly with TSMC. N3E and N4P Node Certification T...
- 26 Oct 2022
RF Engineering: μWaveRiders: Cadence AWR Design Environment V22.1 Software Release Highlights

TeamAWR

The Cadence AWR Design Environment V22.1 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.
- 26 Oct 2022
Computational Fluid Dynamics: On-Demand Webinar - Reduce Ship Fuel Emissions and Costs Through CFD Optimization

AnneMarie CFD

Ship designs, made in CAD software, are becoming more complex every day, and CFD tools have become commonplace to optimize vessel design and reduce lifetime fuel emissions and costs as much as possible.
- 26 Oct 2022
Computational Fluid Dynamics: Women in CFD with Shi Yee Lim

Veena Parthan

The Women in CFD series highlights the career expedition of women in computational fluid dynamics (CFD). For this article, I spoke with Shi Yee Lim, Principle Product Engineer at Cadence, to learn a little about herself, her career journey as a product engineer, and a few tips to the women in or interested in CFD out there!
- 26 Oct 2022
Cloud: For Advanced Chip Design, It’s Time To Go Cloud-First

Mahesh Turaga

EDA in the cloud is on the cusp of mass adoption. Semiconductor companies big and small are today embracing SaaS EDA design and discovering significant productivity and scalability benefits in doing so. This wave of cloud adoption is being driven by...
- 25 Oct 2022
Breakfast Bytes: Jasper User Group 2022: Ziyad's SOTU

Paul McLellan

This year's Jasper User Group meeting took place last week. As usual, the meeting was opened by Ziyad Hanna's presentation on the state of the formal. This year, he titled his presentation Formal Verification in the Era of Domain-Specific Computing. ...
- 25 Oct 2022
Verification: DisplayPort (DP) Tunneling over USB4

tfox

USB4 is an industry standard that tunnels three different protocol specifications (PCIe, USB3 and DisplayPort) serially to a destination. DisplayPort (DP) tunneling over USB4 means DP protocol packets are converted into USB4 protocol packets and transferred over its fabric to a destination. Before the USB4 router sends the packets to its destination, they are converted back to DP protocol packets. In sum and substance…
- 24 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

Good morning and welcome to the last full week of October. Before we plunge into November, let's review what happened at Fidelity CFD last week. From the Blogs Streamline Reading and Writing Files from Fidelity Pointwise For a CFD solution, a CA...
- 24 Oct 2022
Breakfast Bytes: IEDM and RISC-V Summit 2022 Previews

Paul McLellan

There are two big events coming up in the first couple of weeks of December. IEDM is in San Francisco from December 3-7 (the conference proper starts on the 5th, with tutorials and short courses at the weekend. See below for more details). The follow...
- 24 Oct 2022
Verification: Demystifying PCIe Lane Margining Technology

mrana

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology since then. With the doubling of the bandwidth from 8 GT/s to 16 GT/s per Lane in formulating the PCIe 4.0 specifications, there arises the need-to-know overall link health as channels are pushed near operating limits by frequency doubling. By link health I mean -how much signaling margin is available in the design to squeeze out full…
- 21 Oct 2022

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