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Join me, Sandeep Nasa, Senior Principal Education Application Engineer, in our free technical training webinar and discover how the Cadence Protium X3 simplifies your debugging process. We'll show you how FullVision on Protium X3 lets you dump all design signals at once, eliminating the need for multiple recompilations.

What You’ll Learn:

• Enabling and using FullVision on the Protium X3 system
• Key commands…

In recent posts, we've explored the foundational aspects of Time-of-Flight (ToF) technology and the critical role of Tensilica Vision DSPs in efficiently processing and decoding ToF sensor data. We then delved into how Artificial Intelligence (AI) significantly enhances ToF applications, from improving depth quality with denoising to enabling advanced scene understanding for object, gesture, and facial recognition. Now…

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe and CXL?, Verification of Integrity and Data Encryption (IDE) for PCIe Devices, and Verification of Integrity and Data Encryption (IDE) for CXL Devices, this blog focuses on CXL3 IDE verification changes from CXL2.0.

The CXL 3.0 and CXL 3.1 specifications build on the security features…

Let's face it—when most of us hear "partition," we think of land disputes, family feuds, or that one cousin who insists on measuring every square inch of their share.

However, in the world of chip design, partition-based synthesis (PBS) is less about drama and more about design harmony.

Ever feel like you're stuck in a loop, optimizing the same logic block over and over—like déjà vu with a side of…

Imagine you've just built your dream home. You’ve double-checked the plumbing, inspected the wiring, and everything feels perfect. But as you’re about to move in, you find leaks in the plumbing and sparks flying from the wiring. It's a nightmare scenario, right? This is exactly what happens to engineers when they face power integrity issues late in the design cycle. These aren't just backend problems—they're design-time…

While many electronic design companies can standardize on a single vendor workflow for PCB design, not all can. OLogic, Inc., a Silicon Valley consulting group specializing in robotics, IoT, and consumer electronics, must be flexible in the tools they use to design PCBs because some clients require the use of a specific design tool. At CadenceLIVE 2025, Jasmine Vital…

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data, intellectual property …

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation (ASTC) and a renowned leader in virtual platforms. The VLAB Works team provides an ultra-high-performance Virtual Development Environment (VDE) and an extensive catalog of virtual fast models.

The addition of this highly talented team and technology builds upon the existing multi-year Cadence and ASTC partnership, which integrated…

PCB design teams are often caught in a repetitive cycle of design and simulation with multiple iterations to meet PCB design constraints. At CadenceLIVE Silicon Valley 2025, Cadence customers Priya Boopalan of ZF, a global technology company supplying advanced mobility products and systems for passenger cars, commercial vehicles and industrial technology, and Gopichandran Annadurai of Formfactor Inc., a leading provider…