Community

On October 27, the Cadence Academic Network organized the 1st Cadence Academic Workshop in Israel. More than 20 professors as well as PhDs and master students from five major Israeli universities attended the workshop at Bar Ilan University. The first...

In this week's Whiteboard Wednesdays video, William Chen deep dives into the implementation of multi-link, multi-protocol PHY.

https://youtu.be/1nQ0XUw7oe4

A couple of years ago, it was clear that the Cadence implementation flow required a from-the-ground-up re-creation. Nobody likes to say their old tools were not as good as they could be, but that is obviously the case when the new ones are better. And...

On Nov. 18 Dr. Patrick Haspel presented at Khalifa Semiconductor Research Center (KSRC) in the United Arab Emirates. The “Open House” event, which was organized by Dr. Mohammed Al-Mulla and Prof. Mohammed Ismail, who is Center Director, was intended to...

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling, meeting power integrity targets, managing voltage drop, and other related challenges. While the solutions aren’t simple, there are emerging techniques that offer some...

I wrote yesterday of how there is a transition going on as system companies discover that they need to do their own semiconductor design if they are to have products that are differentiated from their competition. To control their destiny, they need to...

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer to infusing the chip design process with greater efficiency.

“Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during a keynote...

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies and methodologies at universities and to foster contacts to the local aligned companies. We know that students either work already at these companies, or will be...

Last year Dan Nenni and I wrote a book on the semiconductor industry through the ages called Fabless. Actually I did most of the writing and I think Dan thought he had it easy. He just had to get contributed sections from all the companies in the industry...

Cadence India organized the 10th edition of the Cadence University Program’s flagship initiative - Cadence Design Contest, in 2015. Launched in 2006, the Cadence Design Contest provides engineering students with an opportunity to showcase their talent...

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University Program and the first such initiative of this kind. In this contest, students are provided with a project problem statement along with a detailed outline and parameters...

To support academia using the latest industry-standard tools, Innovus™ Implementation System has been made available to universities. If you want to use Innovus Implementation System, please contact the Cadence university partner in your region or write...

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses on the digital front-end design tools, which means synthesis, test, and power. Almost any semiconductor seminar has power as one of the main themes. Five or ten years...

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker.

The Allegro Rules Developer and Checker allows you to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment…

For the same reason we "hang up" our phones.

When a layout designer saves a design, they often say "stream out" whereas in most software, such as Word or Powerpoint, this is usually simply called saving the file. As an aside, it is...

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly start DUT integration with Cadence's Verification IP (VIP).

https://youtu.be/rVvq8m9lCNU

In the past few days, there have been many posts on the Internet around Apple planning to remove the 3.5mm audio jack support from the upcoming iPhone 7 to create the slimmest iPhone in history. Given their multiple attempts in the past, it’s perfectly understandable, and for sure the existing Lightning connector is capable of providing this functionality.

From users’ perspective, however, it obviously raises a…

There are two major discontinuities in the last couple of process nodes—FinFETs and multiple patterning—which have changed a lot of the rules for custom design (which doesn't just mean analog, but also standard-cell design and other digital IP). The digital...

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations at OIP and the Technology Symposiums, I knew that they had two. CoWoS and InFO and I knew...well, that's about it, to be honest.

CoWoS (and CoWoS-XL, with...

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence is closed, of course. I’m working on blogs for next week (yeah, right). But I thought I’d put out a fun blog. This has nothing to do with EDA or the semiconductor ecosystem...

First things first. Voltus and Voltus-Fi are two separate products. They are both used for EMIR analysis, Voltus for digital design and Voltus-Fi for analog design (or custom transistor-level digital), or, in conjunction with with Voltus for mixed-signal...

Here is my report from the most recent IEEE 802.3 standards meeting, which was held in Dallas during the week of November 9.

The big news is that work on 50G Ethernet is now about to start. The 25G 802.3by project will soon be ending and plans are afoot for the team working on 802.3by to start thinking about 50G Ethernet.

The 802.3bs 400G project has adopted technology for 50G per lane operation. So it follows…