• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      masamasa
      masamasa 139 Points
    • 2
      excellon1
      excellon1 127 Points
    • 3
      steve
      steve 100 Points
    • 4
      avant
      avant 76 Points
    • 5
      DavidJHutchins
      DavidJHutchins 75 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Global/Local Variables depending on different operation modes

    Category: Custom IC Design

    By ayayla

    •

    updated over 2 years ago by ShawnLogan

    1 replies • 1543 views
  • Discussion

    Where can i find the analog modeling group or community ?

    Category: Mixed-Signal Design

    By sharifsharif

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6394 views
  • Discussion

    Proper Timing Analysis using Innovus (and Genus)

    Category: Digital Implementation

    By Anas2023a95

    •

    updated over 2 years ago by DimoM

    5 replies • 35463 views
  • Answered

    IPC-356 Error

    Category: Allegro X PCB Editor

    By Krutik

    •

    updated over 2 years ago by oldmouldy

    1 replies • 7372 views
  • Discussion

    Error : lps_1801 elaboration : *E,MTOMDU : More than one unit matches 'TESTBENCH'

    Category: Functional Verification

    By Zero00

    •

    updated over 2 years ago by Zero00

    6 replies • 5204 views
  • Discussion

    Noise analysis of a TIA

    Category: Custom IC Design

    By TUKA

    •

    updated over 2 years ago by TUKA

    7 replies • 9122 views
  • Suggested Answer

    There is a BUG in the skill command axlGetParam("artwork:VCC")?? Solve it.

    Category: Allegro X Scripting - Skill

    By aarom

    •

    updated over 2 years ago by Ejlersen

    2 replies • 1693 views
  • Discussion

    Creating Virtuoso views of standard cells from LEF, GDS, and spice views

    Category: Custom IC SKILL

    By matangk2

    •

    updated over 2 years ago by matangk2

    2 replies • 9221 views
  • Discussion

    how to measure eye diagram on a data signal triggered on a self-triggered clk signal

    Category: Custom IC Design

    By a048

    •

    updated over 2 years ago by a048

    11 replies • 12775 views
  • Discussion

    converting standard cell library from cbd to OA on newer 6.1.8 setups

    Category: Custom IC SKILL

    By matangk2

    •

    updated over 2 years ago by matangk2

    6 replies • 10216 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information