• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      Aurel B
      Aurel B 69 Points
    • 3
      AC20250829806
      AC20250829806 60 Points
    • 4
      oldmouldy
      oldmouldy 55 Points
    • 5
      Hoangkhoipcb
      Hoangkhoipcb 50 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,685 Points
    • 3
      eDave
      eDave 10,301 Points
    • 4
      ShawnLogan
      ShawnLogan 9,700 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Printing to PDF from Allegro Design Entry CIS

    Category: PCB Design

    By Goblin59

    •

    updated over 15 years ago by Ejlersen

    5 replies • 16035 views
  • Discussion

    eco route

    Category: Digital Implementation

    By spach

    •

    updated over 15 years ago by spach

    2 replies • 14981 views
  • Discussion

    Request sucess story of Cadence SiP SI or good case.

    Category: Allegro X APD

    By Luke Park

    •

    updated over 15 years ago by TeamAllegro

    1 replies • 13478 views
  • Discussion

    Moderator - help!

    Category: PCB Design

    By hpattie

    •

    updated over 15 years ago by archive

    3 replies • 708 views
  • Discussion

    Problem with Constraints

    Category: PCB Design

    By Trivedi

    •

    started over 15 years ago

    0 replies • 12630 views
  • Discussion

    Controlling Cadence Design files (.dra, .brd, .mcm, .sip) using MKS

    Category: PCB Design

    By britinor

    •

    updated over 15 years ago by britinor

    2 replies • 14993 views
  • Discussion

    negative delay backannotation

    Category: Digital Implementation

    By thescreen

    •

    updated over 15 years ago by thescreen

    1 replies • 19493 views
  • Discussion

    Unable to descend into verilogA view

    Category: Custom IC Design

    By Ramya Deepika

    •

    updated over 15 years ago by skillUser

    1 replies • 14663 views
  • Discussion

    SKILL CODE OF MASTER Pcell

    Category: Custom IC SKILL

    By Sabyasachi

    •

    updated over 15 years ago by skillUser

    3 replies • 15556 views
  • Discussion

    Part-table and bodies versions

    Category: Logic Design

    By DominiqueP

    •

    started over 15 years ago

    0 replies • 13390 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information