• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Aurel B
      Aurel B 59 Points
    • 2
      AC20250829806
      AC20250829806 50 Points
    • 2
      SD20251126912
      SD20251126912 50 Points
    • 2
      SM202511279440
      SM202511279440 50 Points
    • 5
      excellon1
      excellon1 35 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,645 Points
    • 3
      eDave
      eDave 10,261 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,488 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Sparse array error

    Category: Functional Verification

    By abhingp01

    •

    updated over 16 years ago by deniseweisley

    7 replies • 16122 views
  • Discussion

    Transulating a (.MAX) design to (.BRD)

    Category: PCB Design

    By Carvey

    •

    updated over 16 years ago by Carvey

    2 replies • 13238 views
  • Discussion

    Get selected nets from Navigator in IC61

    Category: Custom IC SKILL

    By Yaosan

    •

    updated over 16 years ago by Yaosan

    2 replies • 14318 views
  • Discussion

    Assura RCX fails

    Category: Custom IC Design

    By pitter

    •

    updated over 16 years ago by pitter

    12 replies • 21015 views
  • Discussion

    Netlist mismatch between schematic & .brd file

    Category: PCB Design

    By girish

    •

    updated over 16 years ago by Khurram

    4 replies • 1967 views
  • Discussion

    Simulation data storage directory

    Category: Custom IC Design

    By piters

    •

    updated over 16 years ago by tkhan

    2 replies • 14639 views
  • Discussion

    Adding a pad to a footprint? - in Allegro

    Category: PCB Design

    By JGeens

    •

    updated over 16 years ago by JGeens

    4 replies • 3619 views
  • Discussion

    Working with Scratch Cellview

    Category: Custom IC SKILL

    By Yaosan

    •

    updated over 16 years ago by annegry12

    3 replies • 16440 views
  • Discussion

    aligning dxf import with grid

    Category: PCB Design

    By stellar

    •

    updated over 16 years ago by Khurram

    7 replies • 15899 views
  • Discussion

    import OpenAccess to Cadence Virtuoso and do LVS check

    Category: Custom IC Design

    By shva

    •

    updated over 16 years ago by Quek

    3 replies • 15661 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information