• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      eDave
      eDave 60 Points
    • 2
      MZ20250602835
      MZ20250602835 51 Points
    • 3
      Aurel B
      Aurel B 41 Points
    • 4
      steve
      steve 40 Points
    • 5
      ABIKRISHNA
      ABIKRISHNA 35 Points
  • Leaderboard

    • 1
      steve
      steve 17,769 Points
    • 2
      oldmouldy
      oldmouldy 13,705 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,710 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Calculator error on arithmetic operation on the reading of digital bus

    Category: Custom IC Design

    By delgsy

    •

    updated over 3 years ago by FormerMember

    2 replies • 9624 views
  • Discussion

    LayoutXL creating auto connectivity of custom cell

    Category: Custom IC Design

    By MattTseng

    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 9868 views
  • Discussion

    Layout Cannot Show PDK Instance Graph

    Category: Custom IC Design

    By ovicovic

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 11166 views
  • Discussion

    CDF Parameter change

    Category: Custom IC SKILL

    By Genas

    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 12652 views
  • Discussion

    About finding the cellname of .oa files

    Category: Custom IC Design

    By lingtao jiang

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9005 views
  • Discussion

    Re: command line to select psf directory to allow DC annotation on schematic

    Category: Custom IC Design

    By slim15

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9359 views
  • Discussion

    [Innovus] create_generated_clock giving strange error TA-152

    Category: Digital Implementation

    By Nader Fathy

    •

    updated over 3 years ago by Nader Fathy

    9 replies • 16696 views
  • Discussion

    Installscape stops downloading

    Category: Custom IC Design

    By a2tech

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 8892 views
  • Suggested Answer

    Populate Allegro PCB template with attributes from a capture schematic title block

    Category: Allegro X PCB Editor

    By excellon1

    •

    updated over 3 years ago by Manfred1

    3 replies • 11359 views
  • Discussion

    VerilogA SR Latch with digital output

    Category: Custom IC Design

    By delgsy

    •

    started over 3 years ago

    0 replies • 11034 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information