• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      avant
      avant 55 Points
    • 2
      HP20260601263
      HP20260601263 50 Points
    • 3
      JV202605125312
      JV202605125312 30 Points
    • 4
      FK202606088435
      FK202606088435 27 Points
    • 5
      RM202605273230
      RM202605273230 25 Points
  • Leaderboard

    • 1
      steve
      steve 17,869 Points
    • 2
      oldmouldy
      oldmouldy 13,830 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    What's wrong?

    Category: Custom IC SKILL

    By Martinsh

    •

    updated 9 months ago by mbracht

    1 replies • 1079 views
  • Discussion

    How to convert a shape to a bondfinger and add a wirebond?

    Category: Allegro X APD

    By SaiPavanl

    •

    started 9 months ago

    0 replies • 2758 views
  • Not Answered

    Unexpected Schematic Page Change After Using Allegro Placement in OrCAD X 24

    Category: Allegro X PCB Editor

    By VKPA

    •

    updated 9 months ago by vidhyaparameswari

    4 replies • 3166 views
  • Not Answered

    Ultra Librarian Problem

    Category: Allegro X Capture CIS

    By JS20250331352

    •

    updated 9 months ago by oldmouldy

    2 replies • 1413 views
  • Discussion

    stb results different when iprobe placed at different location of the loop

    Category: Custom IC Design

    By a048

    •

    updated 9 months ago by Frank Wiedmann

    3 replies • 3207 views
  • Suggested Answer

    After annotate facing issues.

    Category: Allegro X Capture CIS

    By Edit slide getting closed

    •

    updated 9 months ago by Edit slide getting closed

    2 replies • 1330 views
  • Answered

    update layout creates a Rectangle "Board Geometry/Top_Room" that cannot be removed

    Category: Allegro X PCB Editor

    By JC202409239850

    •

    updated 9 months ago by John T

    23 replies • 8410 views
  • Discussion

    giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

    Category: Custom IC Design

    By GS202507021424

    •

    started 10 months ago

    0 replies • 493 views
  • Discussion

    Issue about using SkyWater130 and Genus

    Category: Digital Implementation

    By SR202412023415

    •

    started 10 months ago

    0 replies • 3261 views
  • Discussion

    Syntax help with hiCreateMLTextField

    Category: Custom IC SKILL

    By psill00

    •

    updated 10 months ago by Aurel B

    3 replies • 3279 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information