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Breakfast Bytes: CDNLive India 2019: NXP and More

Paul McLellan

Last week I covered Day 1 of CDNLive India. Today it is the turn of verification and PCB/system. With a digression to India's unusual time zone. Day 2 On Thursday, August 29, there were tracks for Advanced Verification Methodology, Performan...
- 10 Sep 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis

kfullerton

If you’ve ever seen a great magician at work, you know that their talent lies in making the impossible look easy. That’s what we have done with Electromagnetic (EM) Analysis in the Virtuoso RF Solution. If you have struggled with cumbersome EM integrations in the past, read further to know what new we have in store for you.
- 9 Sep 2019
Breakfast Bytes: HOT CHIPS: In-DRAM Compute

Paul McLellan

Something that has been discussed for years is the fact that we could add processors to DRAM memory pretty cheaply if we could work out what to do with them. Usually, when people suggest this, they don't really think it through. They are assuming...
- 9 Sep 2019
Verification: Dimensions to Verifying a USB4 Design

Neelabh

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled…
- 8 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 8th September 2019

Paul McLellan

https://youtu.be/AvimlRMDZng Made at Cadence parking lot (camera Steve Brown) Monday: Labor Day Tuesday: HOT CHIPS: The Tesla Full Self-Driving Computer Wednesday: Conformal Litmus Thursday: Ten Reasons to Attend CDNLive Israel Friday: CDNL...
- 8 Sep 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之五 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：启用约束驱动设计高效的互连提取一旦物理layout完成（或者至少串行链路差分对的布线完成），就可以进行布局后验证。需要决定使用多大的带宽进行模型提取。为了评估这一点，需要考虑通过链路传递的信号。 PCI Express Gen 4的规格是指上升时间约为22ps，测量值为10%至90%。将上升时间与信号带宽相关联的经典表达式是： BW (GHz) =350 / Trise (ps) 对于PCI Express Gen 4来说，我们首先考虑的是至少16 GHz...
- 6 Sep 2019
Breakfast Bytes: Pervasive Intelligence

Paul McLellan

The biggest change in technology over the last five or ten years is the sudden kicking into gear of artificial intelligence. I'm sure that you are aware of this. Many people have pointed out that there has been more development in the field since...
- 6 Sep 2019
Breakfast Bytes: CDNLive India 2019: Mediatek and More

Paul McLellan

If you live in California, as I do, then India is a long way away. It is 11½ hours time difference, for a start. Air India has a direct flight from San Francisco to New Delhi (over 16 hours) but since CDNLive is in Bangalore, that is not ...
- 6 Sep 2019
Analog/Custom Design: Virtuosity: Support for Stacked Devices in Modgen

Aneesh Shastry

This blog provides an overview of the support for stacked devices in Modgen. This feature makes it easy for you to visualize and edit devices in highly-complex designs, which, in turn, helps achieve higher circuit performance goals in advanced node PDKs. Read the blog post to know more about how to work with stacked devices in Modgen.
- 6 Sep 2019
Academic Network: Cadence and the Academic Network Support Design Contests in the Asia Pacific

Tracy Zhu

Design contests are a unique way for students to get hands-on experience using Cadence® tools, while in a fun and competitive environment. It is important to the Cadence Academic Network to support design contests so that we can help the nex...
- 5 Sep 2019
Breakfast Bytes: Ten Reasons to Attend CDNLive Israel

Paul McLellan

CDNLive Israel is coming up later this month on September 18 at the David Intercontinental in Tel Aviv. I will be attending as usual so you can expect some Breakfast Bytes posts later in the month. 1. A Day Dedicated to Your Interests As al...
- 5 Sep 2019
Breakfast Bytes: Conformal Litmus

Paul McLellan

One of the earliest science experiments I can remember doing was crushing red cabbage in a mortar and pestle with some sort of alcohol. The resulting purple liquid would turn red in acid and blue in alkali. True litmus is not extracted from red cabba...
- 4 Sep 2019
System, PCB, & Package Design : BoardSurfers: PCB Electronics - Component Placement - Get Set and Go!

mrigashira

How do you place components on a PCB design? Manually? Or quickly using automation? Is there a way to rotate or mirror components while placing them? Is there a way to determine the congested areas or the flow within blocks even while placing components? How do you ensure the placed components are aligned? How o you verify all is well with the board? Read on for the answers.
- 3 Sep 2019
System, PCB, & Package Design : IC Packagers: Manufacturing Cross-Hatched Shapes

Tyler

If you use cross-hatched shapes in your package design, you are doubtless aware of some considerations. Namely, if your shape outline is anything but a rectangular outline at a multiple of the hatch line width pattern, and unless it has no objects to...
- 3 Sep 2019
Breakfast Bytes: HOT CHIPS: The Tesla Full Self-Driving Computer

Paul McLellan

On April 22, Tesla held its Autonomy Day. They announced their "Self-Driving Computer" or SDC. (You can read my post from back then in my post Tesla Drives into Chip Design.) I have said several times over the years that I expected that t...
- 3 Sep 2019
Analog/Custom Design: Virtuosity: Device-Level Routing for Advanced Nodes – Trunk-to-Trunk Mesh Routing

Parula

This blog highlights the importance of trunk-to-trunk mesh routing feature for providing customized device-level routing solutions and how it helps layout designers to be more efficient and organized.
- 2 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 1st September 2019

Paul McLellan

https://youtu.be/_DiWWBDQbGc Made at CDNLive India (camera Corrie Callenbach) Monday: HOT CHIPS: Chipletifying Designs Tuesday: Ford: Automotive OEM to Software Manufacturer? Wednesday: CDNLive China 2019 Thursday: HOT CHIPS: Intel Inside Friday...
- 31 Aug 2019
Life at Cadence: Girls Who Code Reflect on Their Summer at Cadence!

Mary Kasik

This summer, 21 tenth- and eleventh-grade girls came to Cadence’s San Jose campus as part of our partnership with Girls Who Code. The Summer Immersion Program lasted seven weeks and provided the girls with a no-cost curriculum introducing them...
- 30 Aug 2019
Life at Cadence: Interns Making an Impact

Eduardos

Being an intern at Cadence was a rewarding and impactful experience that kickstarted my career. I got a firsthand view of life in Silicon Valley working with a tech company. Being an intern at a FORTUNE 100 Best Companies to Work For® came with ...
- 30 Aug 2019
Breakfast Bytes: Labor Day Off-Topic: Have You Been to Suomi?

Paul McLellan

If you've been in the semiconductor, electronics, or mobile business for some time, chances are that you have been to Suomi. At one point it was the leader in mobile phone handsets. You just might not have realized it. It is the Finnish name for ...
- 30 Aug 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing—Row-based Device Placement

Sravasti

In this blog, I will focus on the automated placement step that is powered by an engine tailored specifically to meet the unique requirements and challenges of analog device-level layouts at advanced nodes. The device-level automatic placer lets you place devices and device groups in a constraint and grid compliant manner. You can use the interactive device placement options to place devices semi-automatically.
- 30 Aug 2019
The India Circuit: CDNLive India 2019: And The Best Paper Award Goes To...

Madhavi Rao

What a whirlwind of two months it has been! And it has been totally worth it, with CDNLive India featuring a huge number of customers, fantastic user-authored presentations and insightful keynotes. A more detailed review will follow, but here is the ...
- 30 Aug 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之四 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：IBIS-AMI建模启用约束驱动设计通过构建预布局测试平台，填入相关模型，生成结果逼真的仿真结果，这时候正适合启用约束来驱动和控制串行链路的物理布局。这可能会导致测试平台需要一些改进和迭代，来添加更多的细节，这是可预期的。此时的方法是参数化测试平台的关键元素，扫描它们以量化其对整个接口性能的影响，并限制那些参数以确保我们的设计在完成时满足合规要求。在PCI Express Gen 4的情况下，核心要求是眼图高度至少为15mV，眼图宽度为0.3UI（对于16...
- 29 Aug 2019
Breakfast Bytes: HOT CHIPS: Intel

Paul McLellan

At HOT CHIPS in August, Intel was everywhere. The two announcements that I'm going to cover in this post were Spring Hill and Spring Crest, two deep learning accelerators, Spring Hill for inference and Spring Crest for training. But they also present...
- 29 Aug 2019
System, PCB, & Package Design : BoardSurfers: PCB Design Technique for Designing a Small RF Section in a Digital Board

Surender

Are you designing a 5G or radar application, or for that matter any application, that requires RF components? Are cost, size-reduction, and performance improvement major concerns for you? Most probably they are. Here we talk about an innovative solution for mixed-signal RF designs using Cadence layout editors.
- 28 Aug 2019

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