Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Analog/Custom Design: Virtuosity: Automated Device Placement and Routing - Identifying Device Groups and Topologies

Sravasti

This blog highlights the importance of identifying device groups and topologies in the fully automated device-level placement and routing flow in Virtuoso.
- 1 Aug 2019
Breakfast Bytes: CHIPs: Interns Around the World

Paul McLellan

Cadence has an intern program that goes under the name CHIPs, for college hires and internship programs. I gave some background on it last year in my post CHIPs in the Cadence Cafeteria, and the year before in CHIP: College Hire and Internship P...
- 1 Aug 2019
System, PCB, & Package Design : IC Packagers: Multi-Wire Bonding with Ease Using Cadence IC Packaging Tools

Tyler

When wire bonding, the most common situation remains a single wire from pin to finger. There may be die to die connections as you step down from one die to the next in a stacked die situation (sometimes called a stitch bond, where the wire is tacked ...
- 31 Jul 2019
System, PCB, & Package Design : BoardSurfers: Capturing Design Intent for Automatic Routing in PCB Editor

mrigashira

Imagine you are designing a complex board with thousands of interconnects and all the usual complexities inherent in a dense design that is also highly constrained. Well, it's easy, the 'imagine' part; and you don't even have to try like John Lennon had crooned in his Imagine song, because most probably you are actually designing one right now that is dominated by bussed interconnect. And most probably…
- 31 Jul 2019
Breakfast Bytes: IEEE Unified Power Models

Paul McLellan

Today the IEEE announced the release of IEEE 2416-2019, a standard for unified power models. Last week, I talked to Jerry Frenkil of Si2, the Silicon Integration Initiative, to get the details. As it happens, Jerry joined VLSI Technology a couple of ...
- 31 Jul 2019
Whiteboard Wednesdays: Whiteboard Wednesdays – xSPI Standard Explained

References4U

In this week’s Whiteboard Wednesdays video, Jacek Duda explains the xSPI standard in detail, its uses, and benefits. The xSPI spec is the first to become an official JEDEC standard.

https://youtu.be/6Cr7WuhyMZc
- 30 Jul 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR5 and ICADVM18.1 ISR5 Now Available

Virtuoso Release Team

The IC6.1.8 ISR5 and ICADVM18.1 ISR5 production releases are now available for download.
- 30 Jul 2019
Analog/Custom Design: Spectre Tech Tips: Spectre Local Options

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Years back, we introduced the Multi-Technology Simulation (MTS) solution that allows you to simulate multiple chips in a single Spectre run, with each chip using its own device models, temperature definitions, and technology scaling setups. In the MMSIM 15. 1 (October 2015) release, MTS was made default…
- 30 Jul 2019
Breakfast Bytes: 5G in US vs Rest-of-World

Paul McLellan

While I was in Germany for the Automobil Elektronik Kongress, the results of the 5G auctions were just announced. Four companies paid €6.5B for spectrum. These were in the 2GHz and 3.5GHz bands. A few weeks earlier, the US Federal Communications...
- 30 Jul 2019
定制IC芯片设计 : Virtuoso视频日记: 比较多个测试和共享设置

Yuan Li

今天的博客重点介绍了现在ADE Assembler中提供的新Multi-Test Editor的功能。通过这个博客，我们已经结束了迷你博客系列，其中涵盖了Virtuoso®ADE Assembler, Virtuoso®ADE Explorer, Virtuoso®ADE Verifier和Virtuoso® Visualization and Analysis刚刚发布的有趣的功能。我们希望您发现这些博客很有用。点这里看我们在本系列中介绍的...
- 30 Jul 2019
Verification: Tales from DAC: Altair's HERO Is Your Hero

XTeam

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out…
- 29 Jul 2019
Breakfast Bytes: Ludwigsburg: It's All About Return-on-Investment

Paul McLellan

I attended the Automobil Elektronik Kongress at Ludwigsburg outside Stuttgart. it was the 23rd year that it has run, and the third that I have attended. The atmosphere has been very different at all three. I summarized the changes affecting the autom...
- 29 Jul 2019
Breakfast Bytes: Sunday Brunch Video for 28th July 2019

Paul McLellan

https://youtu.be/-36euXtgU7Y Made at Cadence Summer of Love Party (camera Chad Yee) Monday: Passwords and Multi-Factor Authentication Tuesday: Virtuoso Meets Maxwell Wednesday: Computer Scientist Alan Turing to Be on British £50 Note Thurs...
- 28 Jul 2019
PCB、IC封装：设计与仿真分析: 开放注册：2019 Cadence中国用户大会

SDA China

Cadence中国用户大会 CDNLive China 2019 上海浦东嘉里大酒店 - 2019年8月15日星期四 space 亲爱的用户朋友：一年一度的Cadence全球用户大会CDNLive China 2019即将来到中国！2019年度的CDNLive China 将于8月15日在上海举办，会议将集聚Cadence的技术用户、开发者与业界专家，涵盖最完整的先进技术交流平台，从IP/SoC设计、验证仿真到封装和板级设计的全流程的技术分享, 以及针对汽车自动驾驶、智能感知、语音交互、机器...
- 26 Jul 2019
System, PCB, & Package Design : BoardSurfers: Designing a Rigid-Flex Board Using PCB Editor

mrigashira

Whether you are designing the latest pace-maker or a LED strip, you have definitely pondered awhile about rigid PCBs and flex PCBs. You might have gone through a pile of literature, called up friends who have already done it (after all flex PCBs have been around for more than half a century now), and deliberated with your team to finally settle on a rigid-flex PCB. Well, what had started as a cutting-edge requirement to…
- 26 Jul 2019
Breakfast Bytes: Digital Twins at the Paris Air Show

Paul McLellan

The idea of a digital twin should be easy for anyone in aerospace to understand. After all, pilots learn to fly planes on simulators of various kinds, which are digital twins. There are two main types, the cheaper ones have the cockpit and graphics b...
- 26 Jul 2019
Breakfast Bytes: Galileo Down for a Week

Paul McLellan

You might never have heard of Galileo, the European Union's GNSS, or Global Navigation Satellite System. That's because your phone probably uses the US system known as GPS or Global Positioning System. There are actually four GNSSs: GPS (US),...
- 25 Jul 2019
Computational Fluid Dynamics: Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpress

AnneMarie CFD

Authors: Akio Takamura, Chief Engineer, Honda R&D, and Benoit Mallol, Head of Marine Products & Applications Group, Cadence It is common knowledge that 80% of the throughput time of a CFD simulation is spent on preparation and set-up. ...
- 25 Jul 2019
定制IC芯片设计 : Virtuoso 视频日记: 下一件大事 - ADE Verifier与Cadence vManager合作

Rashmi G

今天的博客重点介绍了ADE Verifier的最新增强功能。这个博客我们每周二和周四发布的迷你博客系列的一部分，以涵盖 Virtuoso®ADE Assembler , Virtuoso®ADE Explorer, Virtuoso®ADE Verifier和Virtuoso® Visualization and Analysis 的刚刚发布的功能。这个有趣的博客系列现在即将结束...... 现在只剩下最后一个博客！所以请继续关注。在我们之前的文章中，我们...
- 24 Jul 2019
Verification: Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Think

XTeam

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud…
- 24 Jul 2019
Analog/Custom Design: Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

Rishu Misri Jaggi

Really, can Virtuoso bind strict? And what does that mean? Read along to find out...
- 24 Jul 2019
Breakfast Bytes: Computer Scientist Alan Turing to Be on British £50 Note

Paul McLellan

Last week the Bank of England announced that the new £50 note will have Alan Turing on it. The current note features James Watt and Matthew Bolton, the pioneers of the steam engine. It was determined early that the new note would continue to fe...
- 24 Jul 2019
Whiteboard Wednesdays: Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

References4U

In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols and announces that you only need one PHY IP to support xSPI, ONFI 4.x and SD standards!

https://youtu.be/cVi4FEpfpY4
- 23 Jul 2019
Breakfast Bytes: Virtuoso Meets Maxwell

Paul McLellan

When I was a postgraduate at Edinburgh University, my office was in the James Clerk Maxwell Building, the JCMB. Maxwell was most famous for Maxwell's Equations, which give the rules for how electrical and magnetic forces interact, and how electromagn...
- 23 Jul 2019
System, PCB, & Package Design : IC Packagers: Correcting Die Orientations and Die Attachments

Tyler

When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong? The most common re...
- 23 Jul 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.