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Latest Blog Posts

  • Breakfast Bytes: The Mercedes Benz Museum and the Invention of the Automobile

    Paul McLellan
    Paul McLellan
    Recently, I was in Stuggart, Germany. This is the home to the headquarters of both Daimler-Benz (or Daimler-Chrysler as it now is) and also Porsche. Both companies have fascinating museums. The thing that makes them especially interesting is that so ...
    • 12 Jul 2019
  • PCB、IC封装:设计与仿真分析: Cadence LPDDR4设计IP通过TSMC 16FFC FinFET 车规工艺验证

    Sigrity
    Sigrity
    本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC”。 space 今年4月份,Cadence宣布其LPDDR4/4X存储器IP子系统通过ISO 26262 ASIL C认证: “楷登电子(Cadence公司,NASDAQ:CDNS)今日宣布,采用TSMC16nm FinFET Compact(16FFC...
    • 12 Jul 2019
  • Analog/Custom Design: Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

    Parula
    Parula
    The Trunk Generation feature is the founding piece that offers incremental productivity improvement with automation over Pin to Trunk, while still providing all the customizable options in the Pin to Trunk flow.
    • 12 Jul 2019
  • Breakfast Bytes: NXP: Can Silicon Valley Really Crack the Automakers' Code?

    Paul McLellan
    Paul McLellan
    The second panel at the recent NXPConnect was about Silicon Valley versus traditional carmakers (OEMs in car industry terminology). The first panel I covered recently in NXP: Self-Driving Cars: What's the Payoff for Carmakers? Can Silicon Va...
    • 11 Jul 2019
  • VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Technology

    Computational Fluid Dynamics: VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Technology

    AnneMarie CFD
    AnneMarie CFD
    Hydrofoils have unleashed the speed of sailing boats since the last two America’s Cups and are exclusively designed with CFD. The French company VPLP Design is at the cutting edge of the hydrofoil concept and has worked with Alex Thomson Racin...
    • 11 Jul 2019
  • 定制IC芯片设计 : Virtuosity: 过滤波形

    Arja H
    Arja H
    在接下来的几周内,Virtuosity和Virtuoso Video Diary博客将重点关注Virtuoso®ADE Assembler, Virtuoso®ADE Explorer 和Virtuoso® Visualization and Analysis中刚刚发布的功能。因为我们有很多有趣的新增强改进和功能可供讨论,我们将在每周的周二和周四各发布一次博客。今天的博客是ADE迷你博客系列的第二篇。本博客将重点介绍现在可用于Virtuoso® Visualiz...
    • 11 Jul 2019
  • Breakfast Bytes: Carry: Electronics

    Paul McLellan
    Paul McLellan
    The last two days I have written about carry in mechanical calculating devices. See my posts Carry: From Logarithms to Mechanical Calculators and Carry: Babbage's Engines. We have similar problems in designing electronics. Most microprocessors d...
    • 10 Jul 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Cloud-Hosted Design Solution – a Full-Service Cloud Offering

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Jeff Critten describes the key benefits of the Cadence® Cloud-Hosted Design Solution in providing a total solution for companies seeking to move entire electronic design projects to the cloud.

    https://youtu.be/CxvvOgo0ZTQ

    • 9 Jul 2019
  • Verification: AMBA Adaptive Traffic Profiles: Addressing The Challenge

    DimitryP
    DimitryP

    Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems…

    • 9 Jul 2019
  • System, PCB, & Package Design : BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture Phase

    mrigashira
    mrigashira
    View the footprints of symbols during design entry in Capture: verify the footprint and land pattern dimension before exporting your design to a board layout tool, such as PCB Editor,
    • 9 Jul 2019
  • System, PCB, & Package Design : IC Packagers: Balance Your Designs with Cadence SiP Layout

    Tyler
    Tyler
    As designs get more complicated, package substrates are seeing more silicon-driven rules and structures. Substrate styles like fan-out wafer level packaging (FOWLP) and elements such as through-silicon vias (TSVs) being injected into the package lay...
    • 9 Jul 2019
  • Breakfast Bytes: Carry: Babbage's Engines

    Paul McLellan
    Paul McLellan
    Yesterday's post Carry: From Logarithms to Mechanical Calculators talked about how carrying was done in the mechanical and electromechanical calculators of my youth. The most famous mechanical calculators ever designed have to be Charles Ba...
    • 9 Jul 2019
  • 定制IC芯片设计 : Virtuoso视频日记:创建和预览激励

    Arja H
    Arja H
    在接下来的几周内,Virtuosity和Virtuoso视频日记博客将重点关注 Virtuoso® ADE Assembler, Virtuoso® ADE Explorer, 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。因为我们有很多有趣新的功能和改进可以分享给您,我们将在每周的周二和周四发布。今天的博客是ADE迷你博客系列的第一篇。本博客将重点介绍我们推出的新表单,以帮助您的设计创造激励。请继续关注更多有趣的ADE...
    • 8 Jul 2019
  • Breakfast Bytes: Carry: From Logarithms to Mechanical Calculators

    Paul McLellan
    Paul McLellan
    I hope you had a great July 4th long weekend if you are in the US...and if you were elsewhere I hope you at least had a good short weekend. Today is the first of three posts on "carry", in the sense you first learned in primary school, whe...
    • 8 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 7th July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/re7U6Rg0MHA Made at Cadence charge station  (camera Sean) Monday: NXP: Self-Driving Cars: What's the Payoff for Carmakers? Tuesday: It's Beyond HOT at ES Design West Next Week Wednesday: Off-topic: Geography Thursda...
    • 7 Jul 2019
  • System, PCB, & Package Design : IC Packagers: Vary Your Assembled Packages, Not Your Databases

    Tyler
    Tyler
    Design variants are a common phenomenon, whether you design package substrates or PCBs. You may source a resistor from multiple vendors, and part of the design flow includes generating a bill of materials (BoM) which lists all the parts that go on a ...
    • 3 Jul 2019
  • Breakfast Bytes: Off-topic: Geography

    Paul McLellan
    Paul McLellan
    It's the day before a holiday so Breakfast Bytes goes completely off-topic as usual. Last time, the Friday before Memorial Day, we went with figures of speech. This time, let's go with maps and geography. Let's see how good your sense of ...
    • 3 Jul 2019
  • System, PCB, & Package Design : BoardSurfers - Guest Roll: Anatomy of a Good Testcase

    Tyler
    Tyler

    BoardSurfers: Cadence Allegro BlogRik Lee, the author of today's post, is a PCB Designer with more than 35 years experience in the PCB industry, 25+ of those with the Cadence® Allegro® tools. Currently working with Samtec, he has previously worked for both Cadence and EMA, focusing on back-end PCB layout tool support. 

    You come across an issue when using the tools, but you don’t understand why. Being able to troubleshoot an issue, and if needed…

    • 2 Jul 2019
  • System, PCB, & Package Design : DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 2 of 2)

    Auromala
    Auromala

     In part 1 of this two-part blog post, we analyzed how you can define a parts lifecycle manager, define and assign lifecycle states to parts, then distribute the latest parts to designers. In part 2, you're the designer and you want to know which parts to use in your design.

    The initial PCB design – how did you come up with it? Doodled it on a piece of paper? Hashed it out in conference room meetings where at least…

    • 2 Jul 2019
  • Breakfast Bytes: It's Beyond HOT at ES Design West Next Week

    Paul McLellan
    Paul McLellan
    There are two famous parties in the EDA world. The Denali Party by Cadence, of course. I'm afraid you missed that one for this year—it is always on the Tuesday of DAC. The second one is the HOT Party organized by Jim Hogan's Heart of Techn...
    • 2 Jul 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: TILP! What’s a TILP?

    kgjudd
    kgjudd
    I have been breathing IC layout design for the last 38 years! Proliferating new Cadence products in the industry has been an enriching experience. Here I come to talk about yet another powerful invention, Virtuoso RF Solution and the underlying concepts. These concepts must be understood by designers who know package design but are new to the Virtuoso RF Solution. Or, the IC layout designers who are doing package design…
    • 1 Jul 2019
  • Breakfast Bytes: NXP: Self-Driving Cars: What's the Payoff for Carmakers?

    Paul McLellan
    Paul McLellan
    I recently attended NXP's Silicon Valley event called NXPConnect. Kurt Sievers, the President of NXP, opened the show by pointing out it was their largest show ever, with over 1500 people attending, over 100 hours of technology lessons, and over ...
    • 1 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 30th June 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/WhHvvmwE9Tw Made at Tsukuda Fruit Stand opposite building 9 (camera Sean) Monday: Intel and PSS...and Simics, a Blast from My Past Tuesday: 12% Is Not Enough: Women in Engineering Wednesday: DAC: Opening Lunchboxes and Clos...
    • 30 Jun 2019
  • PCB、IC封装:设计与仿真分析: IPC-2581标准相较于旧式通用标准的特点及优势

    TeamAllegro
    TeamAllegro
    本文转载自Sierra Circuit网站:https://www.protoexpress.com/。 space 本文中,IPC-2581标准的全行业推进者Hemant Shah将为大家解答关于该标准的常见问题,特别是相较于Gerber和ODB++等旧式标准而言,IPC-2581的优势及特点。 IPC-2581标准的主要优势: 更完备:集GenCAM和ODB++两者为一体; 更智能:为你的设计提供智能数据; 更安全:支持只发送制造数据给PCB制造商; 更高效:你的设计数据可以一路直达工厂...
    • 28 Jun 2019
  • 定制IC芯片设计 : Virtuosity: 运行计划中的新功能 - 第二部分

    NamrataM
    NamrataM
    我在第一部分中写了关于Virtuoso ADE Assembler运行计划功能的最新增强功能。此博客继续关注自IC6.1.7 ISR15以来增加的其他增强功能。
    • 28 Jun 2019
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