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Vision is everywhere. If you look at the number of sensors that are shipped, then vision appears somewhere in the middle (the red bar in the middle of each column on the graph on the left below). But if you look at the amount of data generated then vision...

NVIDIA just released their next-generation GPU architecture called Pascal and a brand-new GPU device, the Tesla P100.

As part of their product promotion of P100 a couple of weeks ago, NVIDIA invited editors and gaming bloggers covering this latest development...

At Cadence we aim to enable our customers’ need to reduce their own design time and effort. That’s why we have worked closely with Hardent to develop a proven and integrated solution for MIPI Display Serial Interface and VESA Display Stream Compression IP. It provides visually lossless compression that reduces bandwidth by up to 3X.

The demonstration of this solution first took place at CDNLive in Silicon…

This year’s Open Server Summit served up plates full of data…if it wasn’t obvious, there’s more data coming. And then more for dessert. So much so that the challenges seem insurmountable to some. Others see huge opportunities, or a need, to disrupt the server market. Or to change the architecture of these systems to better handle new demands.

According to Cisco Systems, annual datacenter traffic…

EDPS, the Electronic Design Process Symposium, always has the second of the two days dedicated to a single topic. This year it was cyber security. The day started with a keynote from Chris Eagle. He is a Senior Lecturer of Computer Science at the Naval...

Yesterday I covered the analysis by ARM and VLSI Research on FD-SOI from the symposium held a couple of weeks ago. Today it is the turn of the people who actually manufacture the wafers to bring us up to date on how things are going. First Samsung, and...

When a presentation makes us think about an industry on a whole new level and rethink potential outcomes for something significant in our lives, it’s a huge success. This year’s CDNLive San Jose was great for both Cadence and the industry, and here’s why.

Overall, 75% presentations were from customers, and great keynotes (details below) engaged the other attendees. The keynotes on the future of the…

In this week's Whiteboard Wednesdays video, Dennis Crespo explains the optional vector floating-point core specifications of the Tensilica Vision P5 DSP.

https://youtu.be/3PMpIw0r1Hs

Virtuoso Video Diary is envisaged to be an online journal that will relay information about Virtuoso videos that are available in the Cadence Online Support Video Library. For IC6.1.7 and ICADV12.2, over a hundred videos on a wide variety of new and exciting Virtuoso features have already been created. Virtuoso Video Diary brings you direct links to these videos and other related material, on regular basis, in your…

Apparently, asking if something is really a thing is really a thing. So, recently, the SOI consortium organized one of their regular symposia and the thing most people in the audience wanted to know is whether FD-SOI is really a thing.

The SOI consortium...

Significant enhancements to the 16.6-2015 Constraint Manager release have been made in the following areas:

•      Tag-based ECSet Mapping
•      Single-Step Method for Creating Class-Class Relationships
•      PCSets and SCSets Difference Reports

Read on for more details ...

Tag-based ECSet Mapping
The process of applying an ECSet to target nets involves mapping the pins in the ECSet to the component pins in design for those…

The members of an orchestra are often great virtuosi on their own instruments, but the conductor - the maestro – is equally important. The maestro has his score on the conductor’s stand to know exactly what is supposed to be played. He explores the individual intonation and assembles the orchestra into a unique sound. Most importantly, he has to verify that every single tone fits the master plan – the score of the musical…

One challenge with standards is the desire to avoid unknowingly incorporating patents into standards in a way that gives the patent holder a monopoly to go after everyone using the standard and demand unreasonable licensing terms.

When I was at VLSI...

Last week Dr. Andrew Kahng came to town. He was at CDNLive, where his presentation Toward New Synergies Between Academic Research and Commercial EDA won the best paper award for the academic track.Then the following day, he presented at the (internal...

For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an Academic Track where seven professors from leading North American universities shared their outstanding work in research and education with the attendees. The Academic Track...

Last Saturday there was a gala event at the Computer History Museum in Mountain View, where this year's fellows were inducted. Cadence had a table since one of the new fellows was Phil Moorby, the inventor of Verilog and Cadence's own first fellow. So...

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues to impact our daily lives, culminating decades of innovation in communications computer imaging. There were 580 exhibiting companies, accompanied by more than 1,160 peer-reviewed papers and more than 13,000 attendees. This years’ edition of Optical Fiber Conference (OFC), the largest optical communications and networking conference…

Normally the Stanford VLAB meets in Menlo Park, but occasionally they make a foray up to the city, as they did last Thursday for a session with Ann Winblad, who was, I believe, the first female venture capitalist. The location of the meeting was kept...

In this week's Whiteboard Wednesdays video, Chris Rowen looks at the future of neural networks and the key emerging trends.

https://youtu.be/0aGA71_DBSU

There are only a few end markets for semiconductors that really drive the technology. Mobile, obviously. But mobile also drives cloud datacenter deployment since our smartphones increasingly split their functionality with big datacenters (the iPhone's...

A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple:

• Items sent to the DUT are added to the scoreboard and stored in its data base.
• Items returned from the DUT (and collected by the monitors) are added to the scoreboard to be matched against the items sent. 

Basically, the matching algorithm…

At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC...

Yesterday I covered the first half of the CASPA meeting last Saturday about memory in China. That was the big picture.

Simon Yang, XMC

The meeting actually opened with Simon Yang, the CEO of XMC, giving a little bit of history. But the bulk of the...

The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification, like how much functional coverage you should use on a particular design. I promised to next talk about signoff, so here it is.

There are two fundamental steps most users apply to sign-off a new design, a functional milestone…

I can't keep away from work. Saturday found me in the Cadence auditorium for the quarterly meeting of CASPA, the Chinese-American Semiconductor Professionals Association. Yes, I have noticed that I am not Chinese, but I once stepped in at the last minute...