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Analog/Custom Design: Virtuoso ICADVM20.1 ISR20 and IC6.1.8 ISR20 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR20 and IC6.1.8 ISR20 production releases are now available for download.
- 1 Sep 2021
Breakfast Bytes: AI Hardware Summit 2021 Preview

Paul McLellan

The AI Hardware Summit is coming up on September 13-16. It will take place in-person at the Computer History Museum. The website for the event says that most presentations will be given in person, but they will all also be streamed for virtual attend...
- 1 Sep 2021
Digital Design: Pegasus: Get your Wings: Pegasus Results Viewer

Sarita Sharma

You will agree with me that the earlier the bugs are caught the better it is for the overall design cost and time. If you have a robust debugging mechanism, the analysis and fixing of errors becomes quite easy. Pegasus Verification System has a robus...
- 31 Aug 2021
Computational Fluid Dynamics: OMNIS - Addressing Today's And Tomorrow's Multiphysics Simulation Challenges - A Focus On Automotive

AnneMarie CFD

Author: Yannick Baux, Product Engineering Director at Cadence Design Systems The automotive industry has been using CFD tools in the design and optimization processes of all parts of the vehicle, from external aerodynamics to noise reduction to...
- 31 Aug 2021
Breakfast Bytes: HOT CHIPS: A Display in Your Contact Lens

Paul McLellan

Is augmented reality (AR) going to be the next big thing? Tim Cook, CEO of Apple, thinks it will pervade our entire lives. But it certainly won't be until we don't have to wear big, heavy, clunky headsets. I was impressed at CES a couple of y...
- 31 Aug 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

I might have to start calling this Last Week in CFD if I don't reserve time on Fridays to share This Week in CFD here. So from the "Better Late Than Never" Department, here's a look at what's in this week's compilation of CF...
- 30 Aug 2021
Analog/Custom Design: SPECTRE 21.1 Release Now Available

SpectreReleaseTeam

The SPECTRE 21.1 release is now available for download at Cadence Downloads.
- 30 Aug 2021
Breakfast Bytes: CadenceLIVE India 2021: Ten Reasons to Attend

Paul McLellan

On September 7 and 8, it is CadenceLIVE India. It will be a digital event. Let me give you a preview of what is coming up and some reasons to attend. As usual, there are keynotes, technical updates, presentations mainly by customers, an expo...and ev...
- 30 Aug 2021
Breakfast Bytes: Sunday Brunch Video for 29th August 2021

Paul McLellan

https://youtu.be/kC1SNcAmVWg Made in Levi's Stadium (camera Gary Bengier) Monday: CadenceLIVE: Xilinx's Thunder-Bus Tuesday: HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions Wednesday: "I'm Doing an Operati...
- 29 Aug 2021
Life at Cadence: Interns Share What Makes Cadence Special

Eduardos

During their time at Cadence, interns work alongside our team of passionate and brilliant employees. Through their summer projects, interns can experience how Cadence is shaping the world of technology including trends like 5G, AI, machine learning, ...
- 27 Aug 2021
Analog/Custom Design: Virtuosity: Have You Joined the Computational Fluid Dynamics Bandwagon Yet?

deeptik

A guest blog to let you know about Cadence’s recent ventures into the world of Computational Fluid Dynamics.
- 27 Aug 2021
Breakfast Bytes: August Update: Stevies, Sales, Mars, Hacking Hotels, and More

Paul McLellan

Can you believe that it's the last Friday in August already? So, time for another monthly update where I cover recent news relating to earlier posts and also smaller stories that don't justify a whole post on their own. This month, this year&...
- 27 Aug 2021
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso ADE AssemblerとVirtuoso ADE Explorerのユーザビリティがさらに向上

Custom IC Japan

アナログ設計環境製品である Virtuoso ADE Assembler と Virtuoso ADE Explorer の最近のリリースでは、ユーザビリティの向上に努めてきました。今回のブログでは、IC6.1.8/ICADVM20.1 ISR13とISR18の間に追加されたこれらのユーザビリティのアップデートの一部を説明します。コーナー用のモデルファイルの表示 ISR13のCorners Setupフォームに、モデルファイルを表示するショートカットが追加されました。モデルファイル名を右クリッ...
- 26 Aug 2021
Breakfast Bytes: A History of Timing Signoff

Paul McLellan

Today, when all timing signoff is done using static timing analysis with a tool such as the Tempus Timing Signoff Solution, you have to be a certain age to remember that static timing wasn't always around. In fact, at VLSI Technology we developed...
- 26 Aug 2021
RF /マイクロ波設計: uWaveRiders:Cadence AWR Design Environmentに統合されたトランスミッションライン計算器

RF Design Japan

　Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。統合されたトランスミッションライン計算器を使用したインプレース設計　AWR Des...
- 26 Aug 2021
中文技术专区: 用自动化工作流程快速精准地实现刚柔结合电路板的 EM 分析

FormerMember

刊登于：actMWJC 《微波杂志》现代电子设备对数据传输速度和更小体积的需求与日俱增，不断推动柔性电路板的发展。刚柔结合印刷电路板（PCB）由刚性母板和柔性电路组成，一些层上的柔性电路会直接连在刚性母板上（图 1）。刚柔结合板的体积更小、重量更轻且成本更低，被广泛用于现代化的电子设备。优越的弯曲度、适合小空间以及低制造成本，这些特点使其成为移动通信产品的理想选择。图 1：刚柔结合电路板刚柔 PCB 的电磁（EM）分析一直都不简单，需要对将电路板弯曲安装到很小的空间这一复杂的过程进行建模...
- 25 Aug 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectreのハイインピーダンスノードチェックの概要

Custom IC Japan

回路チェックは、ハイインピーダンスノード、電源間のリークパス、タイミングエラー、電力の問題、接続の問題、急激なrise/fallといった、典型的な設計問題を解析することができます。回路チェックはDynamicチェックとStaticチェックに分けることができます。Dynamicチェックは過渡解析中に実行されます。Staticチェックはトポロジーチェックでありシミュレーションは必要ありません。このブログでは、Spectreで用意されているハイインピーダンスノードのチェックについて、そし...
- 25 Aug 2021
System, PCB, & Package Design : BoardSurfers: Training Insights: Creating and Applying Spacing Constraint Sets in Allegro Constraint Manager

Sanjiv Bhatia

When designing a PCB layout, all the constraints and design rules must be followed to avoid design issues and ensure that the board works as intended. Constraints are rules that you apply to different objects in your design, nets, and XNets to ensur...
- 25 Aug 2021
Analog/Custom Design: Virtuoso Meets Maxwell: How the Revamped Feature-Intensive Export Die GUI Empowers You

deeptig

Die export has evolved and it’s time to introduce the new look and feel of the GUI alongside the new features added to bring an abstract view to the next level. The GUI has been redesigned to offer improved usability that matches the evolving use model. The new tab-based GUI has also been made scalable to facilitate the inclusion of further options in the future.
- 25 Aug 2021
Breakfast Bytes: "I'm Doing an Operating System, Just a Hobby, Won't Be Big and Professional"

Paul McLellan

30 years ago today, August 25, 1991, an unknown Finnish student sent out what has become a famously low-key email that had a dramatic effect on technology in general, especially data centers and supercomputers. It has to be one of the most important ...
- 25 Aug 2021
Breakfast Bytes: HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions

Paul McLellan

At HOT CHIPS this morning, Dave Ditzel of Esperanto is presenting their latest chip in a talk titled "Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip" I actually had a pre-bri...
- 24 Aug 2021
System, PCB, & Package Design : IC Packagers: New Releases Are Full of New Stuff!

Tyler

This marks our third and final look at the biggest new features in this major update. We’ve already looked at features spanning from performance gains to improvements in the graphical canvas. Updates to the base product and items for the advanc...
- 24 Aug 2021
中文技术专区: 针对GPGPU设计，Cadence RTL到Signoff流程解密

FormerMember

近年来，随着GPU在通用计算领域的高速发展，逐渐将应用范围扩展到图形之外，例如人工智能、深度学习和自动驾驶。这些领域的特点要求GPU在并行处理海量数据的同时提供更高的访存速度和浮点运算能力。在这种计算密集度越来越高的情况下，我们也面临越来越严峻的挑战，比如在后端摆放和绕线阶段的拥塞问题，如何比较精确地在较早阶段考虑物理信息，预测布局变得尤其重要；在并行同步的信号会增多，大量的矩阵运算引入的情况下，Glitch Power占比会显著提高，如何在较前阶段去分析和避免glitch 功耗是我们避不开的难题；同时由于GPU重运算和流水线的设计加上众多旁路分支结构， OCV影响会更加显著，如何评估和解决时钟上OCV是解决时序收敛的关键因素。针对以上GPGPU面临的挑战和痛点，Cadence提供了一整套从RTL到signoff的全流程解决方案。
- 23 Aug 2021
System, PCB, & Package Design : System Analysis Knowledge Bytes: Signal, Power, and Thermal Integrity using Layout Workbench

kmayank

The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence®. In addition to providing insight into the useful features and enhancements in this area, this series aims to...
- 23 Aug 2021
Breakfast Bytes: CadenceLIVE: Xilinx's Thunder-Bus

Paul McLellan

At CadenceLIVE Americas in June, Raghukul presented on Thunder-Bus, a low-latency bridge between Xilinx FPGAs to accelerate system validation. Since Cadence's Protium X1 and X2 are also built using Xilinx FPGAs, Thunder-Bus can be used to co...
- 23 Aug 2021

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