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Breakfast Bytes: OpenROAD: Open-Source EDA from RTL to GDSII

Paul McLellan

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow, using only open-source software. The goal is to go from RTL to GDSII fully automatically. In a leading-edge process node. With zero DRC errors. In less than 24 hour...
- 15 Nov 2019
Academic Network: Successful Speaker Event—Engaging with Professor in Shanghai

Tracy Zhu

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration with the Shanghai Site Technical Talk series, in Cadence Shanghai Office. The talk attracted more than 150 Cadence employees! I organized ...
- 14 Nov 2019
Breakfast Bytes: What Does P≠NP Mean?

Paul McLellan

Recently I wrote about computational software and said that EDA algorithms are all "intractable". That was in the post Computational Software. What does intractable mean? If you know anything about algorithms, you might have heard term...
- 14 Nov 2019
Analog/Custom Design: Virtuosity: Usability Enhancements in the Property Editor

KomalJohar

Goes without saying that the Property Editor is the most frequently used feature of the Virtuoso platform. If you haven’t yet noticed the usability enhancements in the Property Editor, read ahead to know about a few usability enhancements that we have provided in the Property Editor.
- 14 Nov 2019
Breakfast Bytes: Die-to-Die Interconnect: The UltraLink D2D PHY IP

Paul McLellan

One of the big trends that has been happening somewhat below the radar is the growth of various forms of 3D packaging. I noted this at HOT CHIPS in summer, when a big percentage of the designs were not a single big die, but were multiple die in the s...
- 13 Nov 2019
System, PCB, & Package Design : IC Packagers: Plan Your Escape with Modernized Structures

Tyler

Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin then replicate that structure (or pattern of structures...
- 12 Nov 2019
Life at Cadence: Asking Our Employees: What Makes Us Great in Europe?

Eduardos

As the project manager of our global Great Place to Work programs, I’ve had the opportunity to attend the annual Great Place to Work Conference in Greece and Sweden where they’ve announced their top workplaces in Europe the past couple ye...
- 12 Nov 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

Kabir

This is the third blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. To know about the benefits of preprocessing of layout shapes for electromagnetic analysis, read
- 11 Nov 2019
System, PCB, & Package Design : What's in a Name? From Allegro EDM to Pulse in 17.4-2019

Auromala

Allegro EDM (Engineering Data Management) 17.4-2019 is out! So, what's in it for you?
- 11 Nov 2019
Breakfast Bytes: The 2019 Jasper User Group

Paul McLellan

Last week was the Jasper User Group meeting, the biggest annual gathering of formal verification engineers. This is the 13th meeting. Ziyad recalled the first, held at the TechMart, to which about 15 people attended. This year was the sixth since Cad...
- 11 Nov 2019
Academic Network: Exciting Academic News on OrCAD

Anton Klotz

There’s some exciting news about the Cadence OrCAD® Software, especially for academics! Generations of analog designers have used Cadence ® PSpice® Simulator, which is a part of the OrCAD package, as their first analog simulator. Now...
- 9 Nov 2019
PCB、IC封装：设计与仿真分析: 隐藏在PCB设计中的七个DFM问题

TeamAllegro

本文由Cadence的北美经销商EMA Design Automation撰写。 space 当我们完成设计并将其送到制造厂后，如果我们的产品存在大量可制造性设计（DFM）错误，那么便会造成产品搁置。这种情况不仅令人沮丧，而且代价高昂。在项目早期尽早考虑制造问题有助于降低成本、缩短开发时间，并确保设计顺利过渡到生产阶段。相反，若不这样做，便会造成不良后果。凭借多年的行业经验，我们总结了7大妨碍PCB可制造性的主要DFM问题。虽然以下列出的部分内容是设计方面的最佳实践，但还有一些是由制作/制造...
- 8 Nov 2019
Breakfast Bytes: OpenTitan: Secure Boot with a Silicon Root of Trust

Paul McLellan

At HOTCHIPS last year, Google presented its security processor Titan. You can read lots of details at my post Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter. Titan provides a silicon root of trust (RoT) ...
- 8 Nov 2019
Digital Design: Library Characterization Tidbits: Reasons to Start Following This New Blog Series

AbhaRawat

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.
- 7 Nov 2019
Breakfast Bytes: Computational Software

Paul McLellan

This is the third post in a series on computation in EDA and adjacent markets. The previous two were Computation and the Data Explosion and Computational Hardware. All EDA algorithms are computationally intractable, in that it is impossible to ...
- 7 Nov 2019
Academic Network: ECE Master Students of Duke Kunshan University Visited Cadence Shanghai Office

Tracy Zhu

The Cadence Academic Network was very excited to host students from Duke Kunshan University‘s Electrical and Computer Engineering department at the new Cadence Shanghai office on October 25, 2019. Cadence R&...
- 6 Nov 2019
Analog/Custom Design: Virtuoso Video Diary: Click – Take a Snapshot – Smile!

Rashmi G

This blog talks about about the Snapshots feature introduced in ADE Verifier in IC6.1.8 ISR6.
- 6 Nov 2019
Breakfast Bytes: Tempus Power Integrity Solution

Paul McLellan

One of the challenges in leading-edge nodes today is the resistivity of the interconnect. One day, new interconnect materials such as ruthenium (Ru) might help, but for now, we have copper interconnect, which requires a liner made from a relatively h...
- 6 Nov 2019
Verification: Specman: Analyze Your Coverage with Python

teamspecman

In the former blog about Python and Specman: Specman: Python Is here!, we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage these cool Python apps.

Coverage has always been the center of the verification methodology, however in the last few years it gets even more focus as people develop…
- 6 Nov 2019
System, PCB, & Package Design : IC Packagers: Scripting Updates in 17.4

Tyler

If you joined us last week to see the visual changes to be expected when you download 17.4, doubtless the next thing you need to know is how migrating will impact your automation. And, if you’ve installed the software already, you’re one ...
- 6 Nov 2019
Computational Fluid Dynamics: ArianeGroup: Optimization of the Liquid Hydrogen Turbopump of the Vulcain Rocket Engines

AnneMarie CFD

ArianeGroup is the world’s leading designer and manufacturer of rocket launchers, a joint venture equally owned by Airbus and Safran. Their activities cover the entire life-cycle of a space launcher: design, development, production, opera...
- 5 Nov 2019
Breakfast Bytes: Dead Ends

Paul McLellan

Sometimes something comes along that looks like it is a portent of things to come, but then turns out to be a technological dead end. For example, in the 1990s, it seemed that you couldn't go to the mailbox or rent a video without getting an AOL...
- 5 Nov 2019
System, PCB, & Package Design : Cadence OrCAD and Allegro 17.4-2019 is Now Available

AllegroReleaseTeam

Here is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity-enhancing features. With the 17.4-2019 release, you get more intuitive and easy-to-use flows that enable optimized schematic-to-board-to-...
- 4 Nov 2019
The India Circuit: Is Design in India on the Upswing?

Madhavi Rao

The India Electronics and Semiconductor Association (IESA) recently organized a two-day conference on Strategic Electronics, and, not surprisingly, the overriding message was that India needs indigenous chip design and wafer fabrication facilit...
- 4 Nov 2019
Breakfast Bytes: IEDM 2019 Preview

Paul McLellan

Coming up in the beginning of December is the 65th International Electron Devices Meeting (IEDM). The slightly strange name comes about because this is the 65th, meaning it started in the fifties, long before integrated circuits had been invented. In...
- 4 Nov 2019

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