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Breakfast Bytes: Off-topic: Geography

Paul McLellan

It's the day before a holiday so Breakfast Bytes goes completely off-topic as usual. Last time, the Friday before Memorial Day, we went with figures of speech. This time, let's go with maps and geography. Let's see how good your sense of ...
- 3 Jul 2019
System, PCB, & Package Design : BoardSurfers - Guest Roll: Anatomy of a Good Testcase

Tyler

Rik Lee, the author of today's post, is a PCB Designer with more than 35 years experience in the PCB industry, 25+ of those with the Cadence® Allegro® tools. Currently working with Samtec, he has previously worked for both Cadence and EMA, focusing on back-end PCB layout tool support.

You come across an issue when using the tools, but you don’t understand why. Being able to troubleshoot an issue, and if needed…
- 2 Jul 2019
System, PCB, & Package Design : DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 2 of 2)

Auromala

In part 1 of this two-part blog post, we analyzed how you can define a parts lifecycle manager, define and assign lifecycle states to parts, then distribute the latest parts to designers. In part 2, you're the designer and you want to know which parts to use in your design.

The initial PCB design – how did you come up with it? Doodled it on a piece of paper? Hashed it out in conference room meetings where at least…
- 2 Jul 2019
Breakfast Bytes: It's Beyond HOT at ES Design West Next Week

Paul McLellan

There are two famous parties in the EDA world. The Denali Party by Cadence, of course. I'm afraid you missed that one for this year—it is always on the Tuesday of DAC. The second one is the HOT Party organized by Jim Hogan's Heart of Techn...
- 2 Jul 2019
Analog/Custom Design: Virtuoso Meets Maxwell: TILP! What’s a TILP?

kgjudd

I have been breathing IC layout design for the last 38 years! Proliferating new Cadence products in the industry has been an enriching experience. Here I come to talk about yet another powerful invention, Virtuoso RF Solution and the underlying concepts. These concepts must be understood by designers who know package design but are new to the Virtuoso RF Solution. Or, the IC layout designers who are doing package design…
- 1 Jul 2019
Breakfast Bytes: NXP: Self-Driving Cars: What's the Payoff for Carmakers?

Paul McLellan

I recently attended NXP's Silicon Valley event called NXPConnect. Kurt Sievers, the President of NXP, opened the show by pointing out it was their largest show ever, with over 1500 people attending, over 100 hours of technology lessons, and over ...
- 1 Jul 2019
Breakfast Bytes: Sunday Brunch Video for 30th June 2019

Paul McLellan

https://youtu.be/WhHvvmwE9Tw Made at Tsukuda Fruit Stand opposite building 9 (camera Sean) Monday: Intel and PSS...and Simics, a Blast from My Past Tuesday: 12% Is Not Enough: Women in Engineering Wednesday: DAC: Opening Lunchboxes and Clos...
- 30 Jun 2019
PCB、IC封装：设计与仿真分析: IPC-2581标准相较于旧式通用标准的特点及优势

TeamAllegro

本文转载自Sierra Circuit网站：https://www.protoexpress.com/。 space 本文中，IPC-2581标准的全行业推进者Hemant Shah将为大家解答关于该标准的常见问题，特别是相较于Gerber和ODB++等旧式标准而言，IPC-2581的优势及特点。 IPC-2581标准的主要优势：更完备：集GenCAM和ODB++两者为一体；更智能：为你的设计提供智能数据；更安全：支持只发送制造数据给PCB制造商；更高效：你的设计数据可以一路直达工厂...
- 28 Jun 2019
定制IC芯片设计 : Virtuosity: 运行计划中的新功能 - 第二部分

NamrataM

我在第一部分中写了关于Virtuoso ADE Assembler运行计划功能的最新增强功能。此博客继续关注自IC6.1.7 ISR15以来增加的其他增强功能。
- 28 Jun 2019
Analog/Custom Design: Spectre Tech Tips: Spectre APS Save Overview - Part 2

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated…
- 28 Jun 2019
Breakfast Bytes: Aerospace: the View from Paris

Paul McLellan

I was recently at the Paris Air Show. Despite it sounding like the sort of event where you might go and watch the Blue Angels perform, it is actually the biggest aerospace and defense show in the world, and takes place at the relatively small airport...
- 28 Jun 2019
Breakfast Bytes: DAC: Digital Lunch Does Not Mean Finger Food

Paul McLellan

The Cadence lunch on Tuesday was the turn of digital with the panel set to consider Machine Learning and Its Impact on the Digital Design Engineer. The panel was moderated by Professor Andrew Kahng of UC San Diego. The panelists were: Vishal Sarin, ...
- 27 Jun 2019
Breakfast Bytes: DAC: Opening Lunchboxes and Closing Mixed-Signal Verification

Paul McLellan

The analog/mixed-signal lunch at DAC got moved to Monday this year, since we had made the Spectre X Simulator announcement that morning. For details on that, see my post Spectre X: Same Accuracy, New Speed. The topic this year was Closing Analog...
- 26 Jun 2019
The India Circuit: The 5G Revolution: Viewpoints from Qualcomm, NXP, and MediaTek

Madhavi Rao

A few weeks ago, Cadence hosted an interesting panel discussion that talked about how AI is going to impact various industries. Panelists included Prosit Mukherjee from Qualcomm, Sanjay Gupta from NXP, and Rajbir Singh from MediaTek, and was moderate...
- 25 Jun 2019
Whiteboard Wednesdays: Whiteboard Wednesdays – The Reason Why the Vision Q7 DSP Should be in Your Vision and AI SoC

References4U

In this week’s Whiteboard Wednesdays video, Shrinivas Gadkari goes into great detail on the simultaneous localization and mapping (SLAM) algorithm and why floating-point support is important. Support for these features is why the Vision Q7 DSP should be in your vision and AI SoC.

https://youtu.be/XQHRp0GnJpI
- 25 Jun 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Virtuoso RF Solution - Revolution Begins with a Common Goal for One Flow

michaelthompson

I am traveling home from the heart of the revolutionary Boston, Massachusetts, where I attended IMS 2019. It was indeed a fantastic show with a fitting location that has the history of inception of MIT Radiation Labs in early 1940s. These labs were renamed as Lincoln Labs in 1951. It was the birth of the modern microwave theory and design. Many of the 28-volume radiation lab series remain relevant even today with Samuel…
- 25 Jun 2019
Verification: Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2 of 2)

XTeam

Welcome back to this account of the IP Security Panel at the Accellera Luncheon at DAC 2019. We’ve covered who’s seated on the panel and the moderator’s questions in the last installment (link to first blog)—now it’s time to talk about what the audience had to ask.

The first question asked was related to that morning’s keynote speaker, and that speaker’s one criteria for IP developers with…
- 25 Jun 2019
System, PCB, & Package Design : IC Packagers: The Spaces Between Your Dies

Tyler

Die stacks are starting to look more like skyscrapers every year. If your packages involved vertical stacks of components of any kind, then you know there is more involved in stacking your dies than just the components themselves. What about interpos...
- 25 Jun 2019
Breakfast Bytes: 12% Is Not Enough: Women in Engineering

Paul McLellan

At CDNLive EMEA, there was a Women's track and the first presentation was by Elizabeth Donnelly, the CEO of the Women's Engineering Society (of the UK), titled 12% Is Not Enough, Changing Industry to Support Women in Engineering. I should emp...
- 25 Jun 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: Take a Walk on the Wild Side...with Auto-Roaming

Tyler

We have had this question before, so it’s a good one to remind everyone of in case you’re not aware of it. What I usually hear asked is how can you have the tool automatically pan/roam when your cursor gets to the edge of the canvas.

The good news is that this is there today for you; it may just be that you don’t realize it! To make sure that you don’t pan the canvas at times when you don’t intend to, you…
- 25 Jun 2019
Life at Cadence: Cadence: A Great Place to Work—Asia

FormerMember

For the first time ever, Great Place to Work ranked Cadence as the #15 Best Place to Work in Asia. Cadence was chosen from a pool of nearly 1,200 organizations based on how our employees in Greater China, Korea, and India responded to survey question...
- 25 Jun 2019
Academic Network: International Symposium on Physical Design 2019

Kira Jones

The International Symposium on Physical Design (ISPD) contest is a well-known competition in the EDA field, where the main idea is to have EDA companies share the industrial problems they are facing with the academic community to drive practical rese...
- 24 Jun 2019
Breakfast Bytes: Intel and PSS...and Simics, a Blast from My Past

Paul McLellan

One of the newest standards in verification is PSS, the Portable Stimulus Standard. Whereas UVM is focused on verification of blocks and chips, PSS addresses how to do verification at the system level, where there are multiple processors, with multip...
- 24 Jun 2019
Verification: Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2)

XTeam

Figure 1: The panel and crowd
Citizens—the tech world is in trouble. With the ever-expanding size and complexity of chip designs, security hasn’t kept up. Old techniques for securing a design are no longer sufficient—and with IoT devices expanding into every facet of a person’s life, security is more important than ever. The often-joked-about case of someone hacking your refrigerator isn’t strictly a joke—without proper…
- 24 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 23rd June 2019

Paul McLellan

https://youtu.be/6GUoDQkSoLY Made at Paris Air Show (camera Simon Fielding) Monday: Designing a Wi-Fi HaLow Baseband in Less than Six Months Tuesday: DAC: The View from Wall Street Wednesday: Assessing Bias in Computer Vision Systems Thursday: W...
- 22 Jun 2019

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