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Breakfast Bytes: What's Happening in RISC-V Land?

Paul McLellan

Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week before in the Santa Clara Convention Center, but got ...
- 17 Dec 2019
System, PCB, & Package Design : DATA Pulse: Speed up ECAD Part Search in Allegro System Capture

Auromala

Do you often search for parts when creating Allegro System Capture projects? Yes. Do you work with large ECAD libraries? Yes. Do you work with Allegro EDM Library Manager? No. Then this post is for you.
- 16 Dec 2019
Breakfast Bytes: The Most Important Operating System Ever

Paul McLellan

I wrote recently about Brian Kernighan's memoir and history in Brian Kernighan's Memoirs. He was at Bell Labs during the most important period for computer science, when the Unix operating system and the C programming language were creat...
- 16 Dec 2019
Academic Network: 2019 Workshop on Electronic Design Automation in Hsinchu Taiwan

Tracy Zhu

The Cadence Academic Network has been supporting the Workshop on Electronic Design Automation (EDA) in Taiwan since 2016. This year the event was hosted by National Tsing Hua University in Hsinchu on December 7-8, 2019. This year the workshop ...
- 15 Dec 2019
PCB、IC封装：设计与仿真分析: 图文详解：如何在PowerSI中为封装体上添加假性球体和参考层？

Sigrity

本文由Cadence经销商之一的北京耀华创芯电子科技有限公司整理撰写。耀创科技专注于电子设计自动化（EDA）服务，在引进国外先进EDA工具的同时，针对中国市场特殊性，与Cadence公司合作，在国内最早提出了电子设计与数据管理平台概念，开发出具有自主知识产权的电子电气设计集成数据管理平台，极大加速了板级产品的标准化设计流程，覆盖从优选元件选控、协同设计输入、在线检查分析、标准化文档输出及PLM/PDM系统集成，获得业界一致好评。同时提供除软件使用培训之外的项目陪同设计服务，“与客户共...
- 13 Dec 2019
Breakfast Bytes: Known Good Die

Paul McLellan

Do you know what known good die are? Do you know what wafer sort is? Final test? Wafer Sort After a wafer has been manufactured in the fab, it usually (but not always) goes through wafer sort. This uses a special tester to move across the w...
- 13 Dec 2019
Breakfast Bytes: Brian Kernighan's Memoirs

Paul McLellan

If you have ever worked on placement or floorplanning, and probably some other areas of EDA, then you will have heard of "Kernighan and Lin". It's a partitioning algorithm. You might not even have realized that the Kernighan of Kernigh...
- 12 Dec 2019
Breakfast Bytes: System in Package, Why Now? Part 2

Paul McLellan

This post is a continuation of last week's post Multiple Die in Packages. Why Now? That post looked at several of the drivers for system integration increasingly being done using 3D packaging technologies rather than integrating everything o...
- 11 Dec 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR8 and ICADVM18.1 ISR8 Now Available

Virtuoso Release Team

The IC6.1.8 ISR8 and ICADVM18.1 ISR8 production releases are now available for download.
- 11 Dec 2019
System, PCB, & Package Design : IC Packagers: Copy and Paste Refresh in 17.4

Tyler

The most common operations in any tool are probably adding, moving, deleting… plus copying and pasting. That we all are familiar with Control-C and Control-V being shortcuts to these actions speaks to their applicability across tools we use ev...
- 10 Dec 2019
Breakfast Bytes: Cadence at CES 2020: Tensilica Everywhere

Paul McLellan

Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10, 2020, the start of a new decade. I wonder what electronic marvels we will see before 2030 rolls around. We will be in the south hall of the Las Vegas Convention Center (...
- 10 Dec 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part IV

Kabir

This is the fourth blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. This part highlights how EM analysis in Virtuoso is compared with other third-party tools in terms of accuracy, performance, capacity, memory consumption, and usability.
- 9 Dec 2019
Breakfast Bytes: Xcelium Is 50% Faster on AWS's New Arm Server Chip

Paul McLellan

At Re:invent, Amazon AWS announced Graviton 2, their second-generation Arm server chip. In the AWS news blog, written by Jeff Barr, AWS Chief Evangelist, he provides details. Today I would like to give you a sneak peek at the next generation of Arm-...
- 9 Dec 2019
定制IC芯片设计 : Virtuosity: 针对高阶工艺节点器件级布线的工具— 干线-干线网状布线工具

Parula

本博客强调了干线-干线网状布线功能的重要性，它不仅为定制器件级的布线提供了解决方法，还提高了版图设计师们的工作效率.
- 8 Dec 2019
Verification: Cashing the PSS Promises

Sharon

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...
- 8 Dec 2019
Breakfast Bytes: Sunday Brunch Video for 8th December 2019

Paul McLellan

https://youtu.be/3gP0Z02MVps Made at Salinas River State Park (camera Carey Guo) Monday: The Photonics Summit 2019: Hybrid Lasers Tuesday: Cadence to Acquire AWR Wednesday: "If You Can Get Your Ship into Orbit, You're Halfway to An...
- 8 Dec 2019
Breakfast Bytes: System in Package, Why Now?

Paul McLellan

At HOT CHIPS this summer, one of the things I noticed was just how many of the designs being presented were in some form of 3D packaging with multiple die. I wrote about many of them in my post HOT CHIPS: Chipletifying Designs. At last year's HOT...
- 6 Dec 2019
Digital Design: Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells and IO Cells

Aravind R

Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.
- 5 Dec 2019
定制IC芯片设计 : Virtuosity: 针对高级工艺节点器件级布线的工具 – Generate Trunks

Parula

Trunk Generation 创新功能，不仅实现干线自动化，提高生产效率，还提供完整的Pin to Trunk 流程的自定义选项.
- 5 Dec 2019
Breakfast Bytes: Photonics Summit: Lumerical-Cadence Flow

Paul McLellan

James Pond, the CTO of Lumerical, wrapped up the Photonics Summit recently. He started by giving an overview of the Lumerical-Cadence flow but the real focus of his short presentation was creating robust designs using photonics inverse design, or PID...
- 5 Dec 2019
定制IC芯片设计 : Virtuosity: 针对高阶工艺节点的器件级布线工具 — Finish Trunk

Parula

本博客是该系列博客的第一篇，将介绍Finish Trunk 命令，如何实现器件级的布线需求，它并不算是新功能，但可被认为是又一突破性功能.
- 4 Dec 2019
Breakfast Bytes: "If You Can Get Your Ship into Orbit, You're Halfway to Anywhere"

Paul McLellan

I planned on using the 50th anniversary of Apollo 12 as a hook for this blog, but as it happened I was sick that week, so never wrote it, and my post missed its "launch window". Apollo 12 was from November 14 to 24,1969. I wrote ...
- 4 Dec 2019
System, PCB, & Package Design : Search Faster and Smarter in Release 17.4-2019

Rachna2018

Allegro and OrCAD 17.4-2019 products come with the latest version of CDNSHelp. In this post, I will quickly share the changes made in this release, that will make things much simpler and before you realize it, your content searches will give you better results, and you get more done. Or, know more about what ...
- 3 Dec 2019
System, PCB, & Package Design : IC Packagers: The Third Dimension of 17.4 IC Packaging

Tyler

If you’ve run the 17.4 release, you have probably seen two 3D rendering tools – 3D Viewer and 3D Canvas – present in the View menu. Why are there two? That’s a good question, and the answer lies in the type of design you ...
- 3 Dec 2019
Breakfast Bytes: Cadence to Acquire AWR

Paul McLellan

Yesterday Cadence announced that it has signed an agreement to acquire AWR from National Instruments (NI). Cadence will pay approximately $160M and about 110 AWR employees will join us. The acquisition is expected to close in Q1 2020 after regulatory...
- 3 Dec 2019

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