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Whiteboard Wednesdays: Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard

References4U

In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface Group, describes the new DFI 5.0 specification and the enhancements it provides to the Controller/PHY Interface of DDR memory channels.

https://youtu.be/5rfxkt-5T4o
- 8 May 2018
Breakfast Bytes: Legato: Smooth Reliability for Automobiles

Paul McLellan

In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that EDA would "probably not" solve the problems of automotive, since they are totally focused on the leading-edge nodes. Well, that was four years ago, and EDA has got autom...
- 8 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 14th to 18th 2018

Paul McLellan

https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy Le) Monday: Agile Development of Custom Hardware Tuesday: CDNLive EMEA Session Wednesday: TSMC: Mobile, HPC, IoT, Automotive...and Packaging Thursday:&...
- 7 May 2018
Breakfast Bytes: TSMC's Fab Plans, and More

Paul McLellan

The TSMC Technology Symposium took place recently. I grouped all the process and packaging roadmap into my previous post TSMC Technology Symposium 2018. Today I'll look at the rest of what was presented in the morning. Subsequently I'll put t...
- 7 May 2018
Breakfast Bytes: TSMC Technology Symposium 2018

Paul McLellan

This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president of TSMC North America was the MC for the day. Dave kicked off by giving a few statistics about TSMC's business in North America. In Q4 last year, North Ameri...
- 4 May 2018
Verification: Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress, and HyperRAM

XTeam

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM high-speed memory. We also unveiled a new JEDEC Universal Flash Storage 3.0 (UFS) VIP. Together, these three new VIPs allow early-adopters to leap off the starting line in the race to create new, incredible SoCs and IPs incorporating…
- 3 May 2018
Breakfast Bytes: What's For Breakfast? Video Preview May 7th to 11th 2018

Paul McLellan

https://youtu.be/OJRKUHltc1c Coming from Teske's Germania (camera Sean) Monday: TSMC Fab Plans and More Tuesday: embargoed announcement Wednesday: Digital Marketing in EDA Thursday: CDNLive EMEA 2018 Friday: Compromising a Fo...
- 3 May 2018
Breakfast Bytes: The San Jose Tech Museum

Paul McLellan

Last summer, I did a series of posts about technology museums. If you missed them, here are the links: The Intel Museum German Computer Museums British Computer Museums The Computer History Museum Four Early Computers 1&2 and Four Early Com...
- 3 May 2018
Breakfast Bytes: DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s

Paul McLellan

The DDR5 standard has not been finalized by JEDEC, and they are very strict about not allowing anyone to claim DDR5 compatibility until the standard is complete. That is expected sometime this summer. However, getting designs into silicon can't w...
- 2 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Tensilica DSPs, Sensors, and Neural Networks

References4U

In this week’s Whiteboard Wednesdays video, the last in a three-part series, Robert Schweiger closes the loop on the advantages of hybrid sensor fusion platforms in combination with smart sensors. Tensilica DSPs are ideal for low-power, real-time processing of automotive sensors in particular if neural networks are deployed for high-resolution object detection in camera, radar and lidar sensors.

https://youtu.be…
- 1 May 2018
Verification: How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard

Marcgr

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry.

This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5…
- 1 May 2018
Breakfast Bytes: WoW! TSMC Sticks Whole Wafers Together

Paul McLellan

Today it is the TSMC Technology Symposium. As always, Cadence is making several announcements jointly with TSMC. 5nm and 7nm+ This isn't the biggest surprise announcement of the year. Cadence is collaborating with TSMC on 5nm and 7nm+ high-performanc...
- 1 May 2018
Analog/Custom Design: Virtuosity: Preventing Redundant Simulations

Arja H

I'm sure we all might have come across this situation - Not being sure if something has changed in the simulation setup or design so you need to run a new simulation in Virtuoso ADE Assembler to check the results. This simulation run may take hours or even days to complete and it's a sheer waste of time when you realize the results are identical to the previous simulation. It gets even worse when you have a regression…
- 1 May 2018
Analog/Custom Design: Virtuosity: Use Colin Thomson's New RAK to Learn How Legacy Designs Can be Made XL-Compliant

Rishu Misri Jaggi

Are you bringing in a Layout L design, or a design made outside of Virtuoso into Virtuoso Layout Suite XL? If that's your plan, and if you do want to realize the real power of Layout XL, Colin Thomson (Product Engineering Architect, CPG) has captured some very useful insights in his new RAK that runs you through the steps to get this transition right. Read along to know some more about the RAK, how to access it, and why…
- 30 Apr 2018
Breakfast Bytes: AMI for DDR5 Made Easy

Paul McLellan

In a post last week, I covered IBIS and AMI. One big change that is happening is that the DDR5 standard will (indirectly) mandate using AMI models. DDR5 In the DDR5 standard, which is expected to be published in summer 2018, DRAM will ...
- 30 Apr 2018
System, PCB, & Package Design : Reduce Time-to-Market for Your System-level Designs Using PSpice Systems Option

mrigashira

Looking for a technology to simulate analog/digital mix-signal electronics alongside mechanical, hydraulic and thermal parts with real models for realistic results?
- 27 Apr 2018
Analog/Custom Design: Virtuoso IC6.1.7 ISR19 and ICADV12.3 ISR19 Now Available

Virtuoso Release Team

The IC6.1.7 ISR19 and ICADV12.3 ISR19 production releases are now available for download. To find out more, click here…
- 27 Apr 2018
Breakfast Bytes: Some Real Russian Hacking

Paul McLellan

Patrick Wardle and Mikhail Sosonkin were in Moscow for a PHDays (positive hacking). Gianna Toboni of HBO's VICE News was there too, shooting an episode. The program reached out and asked, "Can you hack our producer?" They were prom...
- 27 Apr 2018
Breakfast Bytes: Qualcomm and Arm Drink Their Own Champagne

Paul McLellan

Everyone in EDA is familiar with the phenomenon where the internal testing of a tool all goes perfectly, the initial customer checkout flights of the tool go well. Then when that same customer starts to use the tool for real, on a real design, all so...
- 26 Apr 2018
The India Circuit: 5 Reasons to Submit an Abstract for CDNLive India

Madhavi Rao

Call for Presentations (CFP) for CDNLive India is now open! While this is something that I get excited about every year, I thought it would be a good idea to highlight some of the reasons why you should be excited too. 1. Be seen as an expert CDNLive...
- 25 Apr 2018
Breakfast Bytes: RSA Cryptographers' Panel

Paul McLellan

The RSA Conference is the biggest conference in security. This year there are 50,000 attendees. Yes, security is on everyone's radar, finally. It is in the Moscone center, in all of North, South, and West. Although it feels like the conference is...
- 25 Apr 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Automotive Sensors: Concepts and Trends

References4U

In this week’s Whiteboard Wednesdays video, the second in a three-part series, Robert Schweiger does a deep dive on the technical aspects of the different sensors on a car: camera, radar, and lidar.

For all three sensors the trend is the same: Increased resolution, higher performance per watt, scalability, smaller form factor at of course a lower price. Especially the new generation of high-resolution imaging radars…
- 24 Apr 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (8 of 8)

Sigrity

Automated Compliance Checking With detailed post-layout interconnect in place, and the IBIS-AMI models properly executing, attention can turn to compliance checking for the specific interface of interest, which is PCI Express Gen 4 in our example. Ea...
- 24 Apr 2018
Breakfast Bytes: What's For Breakfast? Video Preview April 30th to May 4th 2018

Paul McLellan

https://youtu.be/Zpui6QhXM_o Coming from The San Jose Tech Museum (camera Sean) Monday: AMI for DDR5 Tuesday: TSMC related embargoed announcement Wednesday: TSMC related announcement Thursday: TSMC Technology Symposium ...
- 24 Apr 2018
System, PCB, & Package Design : Tech Blog Series: Sensitivity Analysis+Optimization — Now That's Formidable!

Ronak Shah

Anyone who designs complex circuits and claims they don’t use the Optimizer on their design is most likely a super-genius with an IQ of 250. Sure, most of you have used the Optimizer on your circuit before. But, have you used it in combination with Sensitivity Analysis? Optimization is just like having infinite monkeys at your disposal. Use it properly and you're The Man, abuse it and you're wasting time and resources…
- 24 Apr 2018

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