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What do India, Singapore, and Hong Kong have in common? Well, I visited them all a couple of weeks ago, that's one thing they have in common. They all drive on the left, that's another. There's a reason for that. They were all ruled by Britain at some...

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks about the challenges in designing automatic speech recognition (ASR) systems for performance, cost, and power consumption.

https://youtu.be/8sy1BKjssSU

It’s only a week before the first event of USB Developer Days, a series of meetings for USB developers, where the USB 3.2 specification will be formally announced. Much like with any recent smartphone announcement, we know pretty much everything about the new standard before it’s formally announced. We know that the big news is the 20Gbps support, twice the performance of the previous (USB 3.1 Gen 2) standard, which…

I went to Bangalore to CDNLive India. It has a different structure from the other CDNLives that I've attended. It takes place over two days but almost nobody attends both days since the topics are different. Day 1 covered digital implementation, front...

Finding a way out of situations is routine in today’s ever changing world—more so in the world of tech. Our problems range from trivial to critical. Mostly, people look for simple solutions that are easy to use. How sometimes a quick note can resolve a nagging problem! And a smart solution with a video simulating steps helps resolve issues even more quickly and satisfactorily. 

This is exactly what we are…

At CDNLive in Bengaluru (fka Bangalore), Cadence announced the Legato solution for smooth memory design. The press release went out that morning, and Vinod Kariat talked about it in the technical keynote. Later, during the technology update, Joy Han did...

This Wednesday was TSMC's OIP Ecosystem Forum, one of two major events that TSMC run each year. The stars of the OIP Symposium are not so much TSMC themselves but their partners, one of whom is Cadence. We presented six papers during the day, and had...

https://youtu.be/mrUIXwMuNy8

Coming from TSMC OIP Symposium, Santa Clara (camera Sean)

Monday: Legato: Smooth Memory Design

Tuesday: CDNLive India 2017 Trip Report

Wednesday: India, Singapore, Hong Kong

Thursday: Using Neural Nets to Make Neural N...

In a recent feature article at Electronic Engineering Journal, Kevin Morris asks Why are Design Tools So Bad? Or...What? Another Bug?

You will have to read the whole piece if you want to see the entire argument, but here's a sort of summary:

CDNLive India concluded last Friday and what an event it was! With 87 paper presentations, six keynotes, an exhibition area, photo booth, Cadence technology pods and more, CDNLive once again proved to be one of the premier industry conferences.

Both...

A quick guide to TSMC processes. There is a 10nm process but very little development is being done at that node. It is like the mad wife kept in the attic like in Jane Eyre. It seems to be primarily for production of the big names in mobile. In general...

In this week's Whiteboard Wednesdays video, Mengjun Leng follows up on last week's video where she introduced the project of evaluating the speed of different deep learning platforms. In this episode, she continues to share the preliminary evaluation results and highlights future work.

https://youtu.be/5JXSdq1wPa8

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort.

We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP…

At the semiconductor level, automotive poses huge challenges due to an experience mismatch. On one hand are the traditional automotive semiconductor companies, who have a deep experience in automotive reliability, but mostly in low-complexity devices...

"It takes a village to raise a child," as the African proverb says. It seems to take a good part of the semiconductor ecosystem to design a 7nm CCIX test vehicle.

CCIX is quite new so here's a little review. It stands for Cache...

There were three keynotes to kick off CDNLive Boston. Tom Beckley gave the Cadence keynote, then Professor Duane Boning from MIT brought us up to date on photonics, and finally Jim Borowick from Medtronics told us how to design a pacemaker.

It is funny...

At HOTCHIPS 2017, we had a special break so we could watch the eclipse. Of course, Cupertino wasn't on the path of totality. We had to share a very limited number of eclipse glasses since the ones the conference had organized were stuck in customs. Since...

https://youtu.be/ljGLKZ0gz8c

Coming from Singapore Botanic Garden (camera Page Teh)

Monday: CCIX, review and an announcement

Tuesday: Why Are Design Tools So Bad? Or Are They?

Wednesday:TSMC OIP Embargoed Announcment

Thursday: A Record...And a C...

For any parasitic extraction tool, there is always a tradeoff between performance and accuracy. If SPICE simulations were billions of times faster then we would use circuit simulation for large designs. In extraction, we typically use what is known...