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Latest Blog Posts

  • System, PCB, & Package Design : IC Packagers: The Spaces Between Your Dies

    Tyler
    Tyler
    Die stacks are starting to look more like skyscrapers every year. If your packages involved vertical stacks of components of any kind, then you know there is more involved in stacking your dies than just the components themselves. What about interpos...
    • 25 Jun 2019
  • Breakfast Bytes: 12% Is Not Enough: Women in Engineering

    Paul McLellan
    Paul McLellan
    At CDNLive EMEA, there was a Women's track and the first presentation was by Elizabeth Donnelly, the CEO of the Women's Engineering Society (of the UK), titled 12% Is Not Enough, Changing Industry to Support Women in Engineering. I should emp...
    • 25 Jun 2019
  • System, PCB, & Package Design : BoardSurfers - Aerials and Bails: Take a Walk on the Wild Side...with Auto-Roaming

    Tyler
    Tyler

    BoardSurfers: Cadence Allegro BlogWe have had this question before, so it’s a good one to remind everyone of in case you’re not aware of it. What I usually hear asked is how can you have the tool automatically pan/roam when your cursor gets to the edge of the canvas.

    The good news is that this is there today for you; it may just be that you don’t realize it! To make sure that you don’t pan the canvas at times when you don’t intend to, you…

    • 25 Jun 2019
  • Life at Cadence: Cadence: A Great Place to Work—Asia

    FormerMember
    FormerMember
    For the first time ever, Great Place to Work ranked Cadence as the #15 Best Place to Work in Asia. Cadence was chosen from a pool of nearly 1,200 organizations based on how our employees in Greater China, Korea, and India responded to survey question...
    • 25 Jun 2019
  • Academic Network: International Symposium on Physical Design 2019

    Kira Jones
    Kira Jones
    The International Symposium on Physical Design (ISPD) contest is a well-known competition in the EDA field, where the main idea is to have EDA companies share the industrial problems they are facing with the academic community to drive practical rese...
    • 24 Jun 2019
  • Breakfast Bytes: Intel and PSS...and Simics, a Blast from My Past

    Paul McLellan
    Paul McLellan
    One of the newest standards in verification is PSS, the Portable Stimulus Standard. Whereas UVM is focused on verification of blocks and chips, PSS addresses how to do verification at the system level, where there are multiple processors, with multip...
    • 24 Jun 2019
  • Verification: Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2)

    XTeam
    XTeam

    Figure 1: The panel and crowd

    Citizens—the tech world is in trouble. With the ever-expanding size and complexity of chip designs, security hasn’t kept up. Old techniques for securing a design are no longer sufficient—and with IoT devices expanding into every facet of a person’s life, security is more important than ever. The often-joked-about case of someone hacking your refrigerator isn’t strictly a joke—without proper…

    • 24 Jun 2019
  • Breakfast Bytes: Sunday Brunch Video for 23rd June 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/6GUoDQkSoLY Made at Paris Air Show (camera Simon Fielding) Monday: Designing a Wi-Fi HaLow Baseband in Less than Six Months Tuesday: DAC: The View from Wall Street Wednesday: Assessing Bias in Computer Vision Systems Thursday: W...
    • 22 Jun 2019
  • Breakfast Bytes: Why Is 5G Such a Big Deal?

    Paul McLellan
    Paul McLellan
    Yesterday was my post What Is 5G? which is the first half of my introductory look at what 5G really is, based on Ian Dennison's DAC presentation 5G Intelligent System Design. Today we pick up where that post left off. As a reminder, a 5G ne...
    • 21 Jun 2019
  • System, PCB, & Package Design : IC Packagers: Constructing Components from Manufacturing Data

    Tyler
    Tyler
    We’ve all been there. The only (or most accurate) data that we have for a component is the manufacturing data from another process. It could be a GDSII file for the top-layer metal of an IC or a Gerber film for the BGA ball pattern. If all you ...
    • 20 Jun 2019
  • System, PCB, & Package Design : BoardSurfers - Aerials and Bails: How to Split a Viastack

    Monika
    Monika

    BoardSurfers: Cadence Allegro BlogToday’s compact and powerful devices require small and high-density PCBs. Tight routing around densely packed components is thus indispensable, but cannot be achieved using conventional blind-buried and through-hole vias. Consequently, stacked vias have become an essential element of contemporary PCB designs. Stacked vias can be used in place of through-hole vias by placing multiple vias exactly over each other, taking…

    • 20 Jun 2019
  • Breakfast Bytes: What Is 5G?

    Paul McLellan
    Paul McLellan
    At the DAC theater, Cadence's Ian Dennison talked about 5G Intelligent System Design. He repeated his presentation internally at Cadence a couple of days later. Plus, I sat next to him at both CDNLive EMEA and DAC, while I signed books and he tal...
    • 20 Jun 2019
  • Verification: Master of ‘e’? Now You Can Prove It!

    teamspecman
    teamspecman

    The knowledge and experience of using Specman/e tells everyone that you have acquired profound verification methodology. But how do you showcase this knowledge to your company, colleagues, and perspective employers? To help you showcase your expertise, Cadence Training Services now offers Cadence Digital Badging.

    A certification test was created for some technologies (including Specman). When you pass the certification…

    • 19 Jun 2019
  • Digital Design: Exploring AI / Machine Learning Implementations with Stratus HLS

    SeanDart
    SeanDart

    A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance for critical parts of the AI process. Imagine you need dramatically improved rate of object recognition in automated-driving applications.

    Implementing an AI application…

    • 19 Jun 2019
  • Breakfast Bytes: Assessing Bias in Computer Vision Systems

    Paul McLellan
    Paul McLellan
    I came across a fascinating document from Facebook on methods to assess bias in computer vision systems. At F8 2019 (their user conference), they highlighted some of the things that they are doing to address labeling bias, algorithmic bias, and more....
    • 19 Jun 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment Options

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Craig Johnson explains the purpose of the Cloud Passport Partners Program and how customers can now connect with authorized and knowledgeable service providers to tackle complex cloud deployment projects.www.youtube.com/watch

    • 18 Jun 2019
  • Breakfast Bytes: DAC: The View from Wall Street

    Paul McLellan
    Paul McLellan
    Jay Vleeschhouwer did his annual...well, he did it last year, too...View from Wall Street in the DAC Pavilion. I've known Jay for years since I spent a couple of years being the person in Cadence who was house-trained on what I could and could no...
    • 18 Jun 2019
  • Analog/Custom Design: Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download.
    • 17 Jun 2019
  • Breakfast Bytes: Designing a Wi-Fi HaLow Baseband in Less than Six Months

    Paul McLellan
    Paul McLellan
    At CDNLive EMEA last month, Stefan Stanic of Methods2Business (M2B) presented The Challenge of Designing a First-TIme-Right Wi-Fi HaLow Baseband in Less than Six Months. WI-FI HaLow is a standard for superior IoT connectivity. Links can be up to 1km,...
    • 17 Jun 2019
  • System, PCB, & Package Design : DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 1 of 2)

    Auromala
    Auromala

     This is the first of a two-part blog post on managing part obsolescence using Allegro® EDM applications.

    In the midst of a periodic bout of decluttering the house, my niece stumbled across some cassettes and looked at them like they were from some prehistoric age. How could I convey the importance of the audio cassette to my niece? She's used to iTunes, YouTube, Spotify, and goodness knows what else. I remember cassettes…

    • 16 Jun 2019
  • Breakfast Bytes: Sunday Brunch Video for 16th June 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/CaIc3qOakxs Made at building 9 elevator (camera Sean) Monday: Cadence Cloud Passport Partner Program Tuesday: Making Trouble in Las Vegas Wednesday: Paris Air Show Thursday: Ericsson Using Virtual Platforms for Dynamic Analysis ...
    • 16 Jun 2019
  • PCB、IC封装:设计与仿真分析: 刚柔板装配与多板系统装配有何不同?

    TeamAllegro
    TeamAllegro
    通常我们考虑多层电路板PCB设计时,往往会想到服务器环境中的电路板机架或游戏平台组合。但是如果我们的典型刚性电路板并不适合多层电路板使用的实体机壳怎么办?我们会愿意付额外的价格来使用柔性电路板吗?如果我们可以将这两者的优点兼而有之呢? 本文中,我们将介绍刚柔组合的优点、性质以及如何更好地满足多层电路板的PCB设计需求。 什么是刚柔结合的PCB? 在标准多层电路板PCB设计中,我们采用电路板概念,将不同功能电路划分到较小的电路板上,并采用各种互连线路将系统放进一个外壳内。 这种标准方法的问题在于...
    • 14 Jun 2019
  • Single-Stop Learning Resource for JasperGold  Formal Verification Platform

    Learning and Support: Single-Stop Learning Resource for JasperGold Formal Verification Platform

    SumeetAggarwal
    SumeetAggarwal
    While Our next-generation cloud-ready JasperGold® Formal Verification Platform features machine learning technology and core formal technology enhancements across all JasperGold apps, and provides industry-leading performance, capacity, usability...
    • 14 Jun 2019
  • Breakfast Bytes: Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now Shipping in Modus DFT Software Solution

    Paul McLellan
    Paul McLellan
    At CDNLive EMEA, Zhan Gao presented her results on cell-aware test. This is the paper she presented at the Latin American Test Symposium (LATS) in Santiago, Chile in March and won the Best Paper award there (see Anton's post on the Academic Network b...
    • 14 Jun 2019
  • Breakfast Bytes: Ericsson Using Virtual Platforms for Dynamic Analysis

    Paul McLellan
    Paul McLellan
    At CDNLive EMEA last month, Ola Dahl of Ericsson presented Dynamic Software Analysis in Virtual Platforms. He described his job as "I work in the 5G network business doing basestations and radios." They have a virtual platform for one of th...
    • 13 Jun 2019
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