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Academic Network: Europractice and Cadence – A Long Fruitful Partnership

Anton Klotz

Those who have studied microelectronics in Europe since 1989 have certainly heard about Europractice and have probably used EDA technologies provided by them. Though most refer to Europractice as an organization, it is actually an EU-funded project, ...
- 12 Jun 2019
Verification: Specman: Python Is here!

teamspecman

Do you know from where Python technology gets its name? It is not from the snake, it is named after the Monty Python comedy group. And indeed, one of the main guidelines behind it is to be fun to use (check out the Zen of Python). Therefore, Python is intuitive, readable, and easy to learn - all of these make it not only fun to use but also highly productive. Does this sound familiar? If you are an e user, it should. Apparently…
- 12 Jun 2019
Breakfast Bytes: Paris Air Show

Paul McLellan

Next week it is the Paris Air Show, the biggest trade show in aerospace and defense. Cadence will be attending for the first time. The show is held at Le Bourget Airport, which you've probably never heard of. Although it was Paris's first air...
- 12 Jun 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett continues his discussion of the unique needs of different types of companies and introduces the specific Cadence® Cloud solutions designed to meet those needs.

https://youtu.be/iTLy4sYQp1Q
- 11 Jun 2019
System, PCB, & Package Design : IC Packagers: A Classic Revisited - Ball Map Spreadsheets

Tyler

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google, and others are becoming more common in EDA, Cadence® SiP has had a great interface since early in the 16.6 release. You, our users, continue to find creative new use...
- 11 Jun 2019
System, PCB, & Package Design : BoardSurfers: Text Labels and Film Views Help Intelligent Designers

Tyler

Last time, I talked about color and visibility as it relates to simplifying your design canvas display to make your work easier. Today, we take the next step forward: using your artwork films to drive what you see on screen, as well as dynamic text labels to help you find objects. We’ll close out with a reminder of how to recycle the time you’ve spent setting up one design across all your designs.
Artwork…
- 11 Jun 2019
Breakfast Bytes: Making Trouble in Las Vegas

Paul McLellan

For years John Cooley has organized what is called the Cooley's DAC Troublemaker Panel. This year, the participants (troublemakers?) were: Naveed Sherwani, CEO of SiFive (a RISC-V implementation company) Joe Costello of Montana (creati...
- 11 Jun 2019
Analog/Custom Design: Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

Parula

The first blog of the series talks about features that are not new but capabilities that are ground-breaking and can support your device-level routing requirements for advanced nodes with the use of the Finish Trunk command.
- 10 Jun 2019
Learning and Support: Single-Stop Learning Resource for Cadence Low Power Simulation

SumeetAggarwal

Since 2006, low power design has evolved from simple shut off and isolation to very advanced design techniques. This evolution is still in full force. The CPF language was introduced in 2005, and the UPF language was introduced in 2006. Cadence suppo...
- 10 Jun 2019
Breakfast Bytes: Cadence Cloud Passport Partner Program

Paul McLellan

Last year at DAC, Cadence announced Cadence Cloud (see my post Cadence Cloud from that day for details). Since then we have announced CloudBurst (see my post CloudBurst: The Best of Both Worlds for those details), and various other foundry-based...
- 10 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 9th June 2019

Paul McLellan

https://youtu.be/T8nSP-oElJM Made at Design Automation Conference (camera Sean) Monday: Spectre X: Same Accuracy, New Speed Tuesday: DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers Wed...
- 9 Jun 2019
SoC and IP: SemiEngineering Article: Why IP Quality Is So Difficult to Determine

TomWong

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends…
- 7 Jun 2019
PCB、IC封装：设计与仿真分析: 线下专家培训第二站：PCB高效设计入门到进阶——第一期之设计环境准备

SDA China

前言大家好，我是Principal Customer Engagement Engineer郑凤仙，从事PCB设计行业十六年，先后受聘于Mitac、华为两家企业。熟悉PCB全流程设计，拥有丰富的PCB设计经验：在PCB设计工作中，做到了“零”设计事故。设计产品包括电脑主板、服务器、路由器等，擅长于PCB精细化设计及质量管控。 PCB设计工作需要具备很强的沟通能力，需要熟悉电路设计、工艺流程、结构设计等领域的基础知识，是一项综合性极高的工作。这几年的工作留给我的感受一直是...
- 7 Jun 2019
Academic Network: Carnegie Mellon University – Real World Engineering Program

Anton Klotz

Cadence San Jose was happy to host a group of undergraduate students from Carnegie Mellon University. Through the Real World Engineering program, students from CMU get the opportunity to visit different companies in Silicon Valley, Pittsbur...
- 7 Jun 2019
Analog/Custom Design: Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations?

NamrataM

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind of feature called point-to-point info balloons. These info balloons provide critical information that you would find handy while working with critical nets to resolve EM violations. Read more...
- 7 Jun 2019
Breakfast Bytes: 1984 Was Published 70 Years Ago

Paul McLellan

If you work in any aspect of tech, one book that you have to have read is George Orwell's 1984. Aspects of the impact of technology on life are always being compared to things in the book. For example, Big Brother watches everyone through TV scre...
- 7 Jun 2019
Academic Network: Cadence Academic Network Expands to Kazakhstan

Anton Klotz

Dear reader, may I ask you, what do you know about Kazakhstan? Do you know that Kazakhstan is the 9th largest country on earth? I It is nearly four times the size of Texas. Do you know that it is between China and the European part of Russia? Kazakhs...
- 6 Jun 2019
Breakfast Bytes: DAC Wednesday: Verification Lunch, Books, and Bagpipes

Paul McLellan

For my coverage of the first two days of DAC, see my posts DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers, and DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali. Verifica...
- 6 Jun 2019
Breakfast Bytes: DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali

Paul McLellan

It was the second day of DAC yesterday. If you were here, you probably saw some of these main events. If not, then read on. I'll tell you what you missed. Thomas Dolby The keynote was Thomas Dolby, probably most famous for his single "She Blinded Me ...
- 5 Jun 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM) – Part 2

References4U

In this week’s Whiteboard Wednesdays video, Amol Borkar continues his discussion on SLAM including the benefits and weaknesses of different implementations and how the Vision Q7 DSP gives you the best performance, power, and capability of handling heavy compute workloads. Must watch!

www.youtube.com/watch
- 4 Jun 2019
System, PCB, & Package Design : IC Packagers: The (Copper) Pillars of Modern Design

Tyler

Wire bonding has been around forever. Flip-chip mounting? That’s been around for a long time as well. Every new generation of packages brings with it new technologies, challenges, and options. Copper pillars have been around for a fair time as ...
- 4 Jun 2019
System, PCB, & Package Design : BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

Tyler

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to thousands of components and pins, degassed and cross-hatched shapes, routing, and everything in between can make the visual depiction of your layout imposing, to put it mildly.

How, then, do you reclaim control? Focus on exactly what you need to see and when you need to see it? Are there ways to simplify determining whether the via you…
- 4 Jun 2019
Breakfast Bytes: DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers

Paul McLellan

The Design Automation Conference is in Las Vegas this year. If you are here and want my recommendations, then see my post Top 10 Reasons to Go to DAC. If you are not here, and want to know some of what you missed, then this post covers a lot of what ...
- 4 Jun 2019
Academic Network: How to Show You’re a Verification Engineer?

Anton Klotz

There is always a need for verification engineers in the microelectronics industry. The costs of verification have long ago surpassed the costs of implementation, but still the focus in academia is on implementation and not too many universities offe...
- 3 Jun 2019
System, PCB, & Package Design : IC Packagers: Dealing with Large Forms in Low Resolution Screens

Monika

Our packages and boards are becoming complex and so are the design tasks we perform and the tools that we use. Although ease of use is the mantra for all our UIs, sometimes a form ends up having too many elements to address the ever-increasing requir...
- 3 Jun 2019

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