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Cadence^®︎ Spectre^®︎ With the DSPF-in-the-middle feature, designers can easily set up complex configurations in the Hierarchy Editor (HED) and run a post-layout mixed-signal simulation with just a few clicks. View this blog to know more.

The growing complexity of electronics in modern cars is driving the automotive industry to adopt even more stringent processes throughout the supply chain. The lack of tools and methodologies to enforce a traceable safety lifecycle and exchange of safety-relevant information has created the need for an integrated design flow that addresses the safety requirements…

For the past few decades, design and verification technology have made great progress. More sophisticated designs are verified with faster simulation and emulation. However, the debug is pretty much the same as 20 years ago. The most bothersome thing for engineers is why there’s no way to automate the process. What engineers typically do is, check the log file and see if there are any errors from verification tools such…

Spectre APS supports dynamically changing errpreset or reltol during a transient simulation. This feature is used by advanced Spectre users to optimize simulation performance when different time windows of the simulation have different accuracy requirements. The use model for this feature is the following:

• tr1 tran stop=10u param=errpreset param_vec=[0 liberal 2u moderate]

The errpreset parameter is not available in…

Scaling chip size and increasing functionality over SoCs has increased complexity and verification time. Verification teams are concerned about the bugs that may have slipped to silicon earlier and their discovery rate. Moreover, completing the verification and achieving the desired coverage is tricky. It looks arduous to complete the verification and meet the time constraints, especially when the specifications change…

2023 is here, and technology trends around Compute Express Link (CXL) and the next generation of AMBA protocols (CHI-E/F) are getting more traction. The biggest challenge of today is the complexity of handling enormous data flow owning to AI, ML, and deep learning applications. To keep up with the pace, new generation interfaces introduce specialized semantics catering to memory disaggregation, cache consistency, techniques…

Well, we know you are busy, but it's time to develop your expertise in the synthesis domain with the Genus Synthesis Solution. How? You can plan to complete the Genus Synthesis Solution with Stylus Common UI training.

The ultimate goal of the Cadence^® Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR)…

DDR5 is the latest generation of the DDR server memory capable of supporting data rates of up to 8800 Mbps which is quite a leap over previous generations of DDR memories. It is used in a wide variety of applications with a huge server, and the data center market is a key driver behind the adoption of the DDR5-based memory systems. As systems are moving towards more CPU cores, higher bandwidth, and more capacity, DDR5…

Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.

What Is a Chiplet?

A chiplet is a tiny integrated circuit (IC) with a well-defined specific functionality. One can relate this to LEGO building blocks for creating large structures.

Why Do We Need a Chiplet…

Embedded DisplayPort 1.5 (eDP 1.5) is an interface standard that is based on the DP 2.0 (DP standard), and it is designed to transport video between the system host, i.e., GPU, and device, i.e., display panel. It supports selective DP 2.0 features and additional features that are designed to conserve power. The diagram below, which is taken from the eDP 1.5 standard, shows a simplified eDP implementation.

Some of the…