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Designers have long recognized the need to analyze the reliability of ICs. Two commonly used approaches for performing reliability analysis include calculating the change in device degradation and relying on safe operating checks in circuit simulators. 

With the advent of the ever-increasing use of ICs in mission-critical applications, the need for reliable reliability analysis has become of paramount importance. Over…

Low-power DDR (LPDDR) SDRAM has been one of the most widely used memories in the semiconductor market today. It is used in a diverse set of applications that span mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and artificial intelligence (AI) applications, just to name a few.

On April 10 and 11, 2024, Cadence hosted the JEDEC LPDDR Task Group, which…

The traditional synthesis process relies on the Wireload models to estimate the delays. This often leads to difficulty in closing timing in the backend, leading to multiple iterations and turnaround time!! Are you ready to trade off PPA results in this fast-growing technology era?

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion makes the design optimization more complex. The real…

Today’s electrical engineers (EEs) are being asked to design increasingly complex products in less time than ever before. To satisfy design requirements and produce designs on schedule, EEs require solutions that let them not only capture design logic, but also run meaningful simulation and analysis, ensuring first-pass success more often.

What is the EE cockpit paradigm? What kind of design checks and analyses…

We all know the benefits of gate-level simulation, but we also all know the pain of trying to run it. Setting up and running GLS on large designs is a huge time sink for engineers—but what if there was a better way? A large team at Northrop Grumman faced this exact issue working on a large ASIC. They found some clever ways to vastly speed up their gate-level simulation, and they shared their experience in a presentation…