• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Community Forums
  3. Cadence Community
Cadence Community
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Search
  • User
Find Other Members ►
Subscriptions
Get email delivery of the Cadence blog (individual posts).
  • Twitter
  • Facebook
  • LinkedIn
  • Google+

Community


Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

  • Exploring Strengths with Personality and Preference Inventory (PAPI) Assessment

    Life at Cadence: Exploring Strengths with Personality and Preference Inventory (PAPI) Assessment

    Ryan Robello
    Ryan Robello
    Written by Pooja Pangoria, Software Engineering Group Director, Bangalore “You alone are enough. You have nothing to prove to anybody.” – Maya Angelou, Poems by Maya Angelou (1978) In today’s world of rapidly changing technol...
    • 20 Jun 2024
  • Virtuoso Studio: Virtuoso ADE Assemblerでシミュレーション履歴に名前を付ける方法は?

    カスタムIC/ミックスシグナル: Virtuoso Studio: Virtuoso ADE Assemblerでシミュレーション履歴に名前を付ける方法は?

    Custom IC Japan
    Custom IC Japan
    当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ、および従来の設計の枠を超えた新しいレベルの統合環境を提供します。このブログシリーズでは、最高のアナログ設計ツールがどのように改良され、困難な設計課題に対応できるようになったかを紹介します。 意味のある名前の使用、グループ化、アイテムの並べ替えは、整理整頓を保つためのよく知られた方法...
    • 20 Jun 2024
  • Socionext Is Tackling SoC Design Challenges

    Corporate News: Socionext Is Tackling SoC Design Challenges

    Tanushri Shah
    Tanushri Shah
    Socionext is an SoC company that has pioneered its business model to help companies achieve differentiation according to their specific needs. The Socionext team collaborates closely with their partners worldwide and delivers complete SoC solutions, ...
    • 20 Jun 2024
  • Podcast: PCB 3.0: It’s All About the Data

    System, PCB, & Package Design : Podcast: PCB 3.0: It’s All About the Data

    NaomiM
    NaomiM

    Data management and PCB design discussions have shifted from the basics of data management to collaboration. OEMs and manufacturers shifting into system design need control of the overall design, but they can’t give up control over their IP and security. Without collaboration, there are gaps in communication and addressing problems takes longer.

    How can mining your own data save time and design cycles? What are…

    • 19 Jun 2024
  • Cyber Security at the Olympics: Protecting the World's Greatest Games

    Corporate News: Cyber Security at the Olympics: Protecting the World's Greatest Games

    Corporate
    Corporate
    The Olympic Games are more than just an international sporting event. They symbolize unity, peace, and the human spirit's triumph over adversity. But behind the scenes, a digital struggle ensues, threatening this global celebration. Cybersecurit...
    • 19 Jun 2024
  • System Analysis Knowledge Bytes - Importance of VRM Modeling in PDN Simulation

    System, PCB, & Package Design : System Analysis Knowledge Bytes - Importance of VRM Modeling in PDN Simulation

    Jasmine
    Jasmine
    This post talks about the role of VRMs in Power Integrity (PI) analysis It discusses the VRM Model types available in Sigrity OptimizePI.
    • 18 Jun 2024
  • VIP Portfolio Expands for Data-Intensive Hyperscale Data Centers, HPC, and AI/ML

    Corporate News: VIP Portfolio Expands for Data-Intensive Hyperscale Data Centers, HPC, and AI/ML

    Corporate
    Corporate

    New additions, including first-to-market VIP for PCIe 7.0, Ethernet 1600G, GDDR7, next-gen HBM, and DFI next-gen HBM, enable fast and comprehensive verification, ensuring SoCs meet specifications for the latest standards protocols

    Cadence recently announced the extension of its Verification IP (VIP) portfolio to include support for new VIP for emerging high-speed interfaces critical in data-intensive domains, such as…

    • 18 Jun 2024
  • Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at Embedded World 2024

    Corporate News: Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at Embedded World 2024

    Corporate
    Corporate
    Cadence Verification and RTL-to-GDS Digital Full-Flow Tuned for Automotive Safety, Quality, and Reliability Requirements At embedded world 2024, Cadence and Dream Chip demonstrated Dream Chip’s latest automotive SoC, which features the...
    • 18 Jun 2024
  • System Analysis Knowledge Bytes - Early System-Level Thermal Analysis

    System, PCB, & Package Design : System Analysis Knowledge Bytes - Early System-Level Thermal Analysis

    Jasmine
    Jasmine
    This post introduces you to the CAD capabilities of the Celsius Thermal Solver. It discusses the steps to run a successful simulation using the Celsius Thermal Solver GUI.
    • 15 Jun 2024
  • The History of Electronics in Sports

    Corporate News: The History of Electronics in Sports

    Corporate
    Corporate
    In today's fast-paced world, technology touches nearly every part of our lives, including sports. Electronics play a pivotal role in athlete performance, training, and even fan engagement. As we gear up for the upcoming Olympics, we wanted to ex...
    • 14 Jun 2024
  • CadenceLIVE Silicon Valley 2024

    Learning and Support: CadenceLIVE Silicon Valley 2024

    ErinGrant
    ErinGrant
    CadenceLIVE Silicon Valley 2024 was a notable event recently held at the Santa Clara Convention Center, drawing a diverse crowd of users, developers, and industry experts. This annual conference showcases the latest advancements in electronic sy...
    • 14 Jun 2024
  • Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

    SoC and IP: Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

    GautamS
    GautamS

    PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low…

    • 14 Jun 2024
  • Virtuoso Studio: 動作点パラメータ値を簡単にレビューする

    カスタムIC/ミックスシグナル: Virtuoso Studio: 動作点パラメータ値を簡単にレビューする

    Custom IC Japan
    Custom IC Japan
    当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ、および従来の設計の枠を超えた新しいレベルの統合環境を提供します。このブログシリーズでは、最高のアナログ設計ツールがどのように改良され、困難な設計課題に対応できるようになったかを紹介します。 全デバイスの動作点パラメータ値をまとめてレビューするという課題に直面したことはありませんか...
    • 13 Jun 2024
  • Reimagine Enterprise Data Center Design and Operations

    Data Center: Reimagine Enterprise Data Center Design and Operations

    Danielle Gibson
    Danielle Gibson
    Ever feel like the only constant in the data center industry is that things are always changing? You’re not alone. From rising densities to evolving environmental policies, there’s never a shortage of change in our field. Navigating this ...
    • 13 Jun 2024
  • Silvus Achieves Faster Tapeout of Advanced RF-MS Chip with Cadence Managed Cloud

    Cloud: Silvus Achieves Faster Tapeout of Advanced RF-MS Chip with Cadence Managed Cloud

    Mahesh Turaga
    Mahesh Turaga
    Silvus Technologies announced the successful tapeout and bring-up of an advanced RF-mixed-signal chip leveraging Cadence tools in the managed cloud environment. This powerful IC boasts an impressive 15 million devices and enables cutting-edge signal ...
    • 12 Jun 2024
  • How Cadence Is Expanding Innovation for 3D-IC Design

    SoC and IP: How Cadence Is Expanding Innovation for 3D-IC Design

    Vinod Khera
    Vinod Khera
    The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...
    • 11 Jun 2024
  • Cyborg Games at Olympics: Fusion of Technology and Physical Prowess

    Corporate News: Cyborg Games at Olympics: Fusion of Technology and Physical Prowess

    Corporate
    Corporate
    Envision a competition where athletes rely on their physical prowess and harness the power of cutting-edge technology. Welcome to Cyborg Games, a groundbreaking addition to the Olympic repertoire that promises to revolutionize how we perceive athletic achievement. This blog will take you on a fascinating journey through the history, technology, and future of the Cyborg Games.
    • 11 Jun 2024
  • Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24

    SoC and IP: Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24

    GautamS
    GautamS
    PCI-SIG DevCon 2024 – 32nd Anniversary

    For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets…

    • 11 Jun 2024
  • Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification

    Analog/Custom Design: Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification

    Andre Baguenie
    Andre Baguenie
    Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera.
    • 11 Jun 2024
  • NV5 Is Optimizing Data Center Efficiency, Performance, and Reliability

    Corporate News: NV5 Is Optimizing Data Center Efficiency, Performance, and Reliability

    Tanushri Shah
    Tanushri Shah
    NV5 is a leading engineering firm at the forefront of designing AI compute data centers. They engineer, commission, and manage various projects, from underwater transmission lines to high-demand AI compute data centers. As the thermal demands of AI c...
    • 10 Jun 2024
  • Electronics Everywhere and AI-Driven Design at IMS

    Corporate News: Electronics Everywhere and AI-Driven Design at IMS

    Corporate
    Corporate
    Imagine a world where everything is electrified. From smart homes to wearable tech, we're already racing toward a future that is seamlessly digitalized thanks to cutting-edge advancements in electronics and artificial intelligence (AI). As our re...
    • 10 Jun 2024
  • Cadence CFD Advances Greener Turbomachinery at ASME Turbo Expo 2024

    Computational Fluid Dynamics: Cadence CFD Advances Greener Turbomachinery at ASME Turbo Expo 2024

    Veena Parthan
    Veena Parthan
    The ASME Turbo Expo 2024 is all about propelling towards a net-zero future in propulsion and power. This year, the focus is on evolving turbomachinery and propulsion technology for net-zero goals, highlighting disruptive technologies, sustainable ecosystems, and a collective push for innovation and sustainability.
    • 10 Jun 2024
  • Virtuoso Studio: How Do You Name Simulation Histories in Virtuoso ADE Assembler?

    Analog/Custom Design: Virtuoso Studio: How Do You Name Simulation Histories in Virtuoso ADE Assembler?

    NamrataM
    NamrataM
    This blog describes an efficient way to name the histories saved by the simulation runs in Virtuoso ADE Assembler.
    • 7 Jun 2024
  • USB4 Version 2.0 – Gen4 Link Recovery

    Verification: USB4 Version 2.0 – Gen4 Link Recovery

    Neelabh
    Neelabh

    USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.

    Here, we take an overview of the Gen4 link recovery mechanism, which is an autonomous process. It is initiated by a router when it encounters uncorrectable error events. These error events could be a timeout error…

    • 7 Jun 2024
  • Chiplet Integration in the Automotive Realm

    SoC and IP: Chiplet Integration in the Automotive Realm

    Reela Samuel
    Reela Samuel

    As technology continues to advance, the automotive industry is rapidly transforming. The integration of chiplets, or small microchips that work together to form a larger, more powerful system, is at the forefront of these advancements.

    This blog post is an excerpt from a presentation at CadenceLIVE 2024 in Silicon Valley by Pratibha Sukhija, Anunay Bajaj, and Ericles Sousa. We will examine the intricate details of chiplet…

    • 5 Jun 2024
<>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information