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Latest Blog Posts

  • CadenceLIVE Silicon Valley 2024

    Learning and Support: CadenceLIVE Silicon Valley 2024

    ErinGrant
    ErinGrant
    CadenceLIVE Silicon Valley 2024 was a notable event recently held at the Santa Clara Convention Center, drawing a diverse crowd of users, developers, and industry experts. This annual conference showcases the latest advancements in electronic sy...
    • 14 Jun 2024
  • Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

    SoC and IP: Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

    GautamS
    GautamS

    PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low…

    • 14 Jun 2024
  • Virtuoso Studio: 動作点パラメータ値を簡単にレビューする

    カスタムIC/ミックスシグナル: Virtuoso Studio: 動作点パラメータ値を簡単にレビューする

    Custom IC Japan
    Custom IC Japan
    当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ、および従来の設計の枠を超えた新しいレベルの統合環境を提供します。このブログシリーズでは、最高のアナログ設計ツールがどのように改良され、困難な設計課題に対応できるようになったかを紹介します。 全デバイスの動作点パラメータ値をまとめてレビューするという課題に直面したことはありませんか...
    • 13 Jun 2024
  • Reimagine Enterprise Data Center Design and Operations

    Data Center: Reimagine Enterprise Data Center Design and Operations

    Danielle Gibson
    Danielle Gibson
    Ever feel like the only constant in the data center industry is that things are always changing? You’re not alone. From rising densities to evolving environmental policies, there’s never a shortage of change in our field. Navigating this ...
    • 13 Jun 2024
  • Silvus Achieves Faster Tapeout of Advanced RF-MS Chip with Cadence Managed Cloud

    Cloud: Silvus Achieves Faster Tapeout of Advanced RF-MS Chip with Cadence Managed Cloud

    Mahesh Turaga
    Mahesh Turaga
    Silvus Technologies announced the successful tapeout and bring-up of an advanced RF-mixed-signal chip leveraging Cadence tools in the managed cloud environment. This powerful IC boasts an impressive 15 million devices and enables cutting-edge signal ...
    • 12 Jun 2024
  • How Cadence Is Expanding Innovation for 3D-IC Design

    SoC and IP: How Cadence Is Expanding Innovation for 3D-IC Design

    Vinod Khera
    Vinod Khera
    The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...
    • 11 Jun 2024
  • Cyborg Games at Olympics: Fusion of Technology and Physical Prowess

    Corporate News: Cyborg Games at Olympics: Fusion of Technology and Physical Prowess

    Corporate
    Corporate
    Envision a competition where athletes rely on their physical prowess and harness the power of cutting-edge technology. Welcome to Cyborg Games, a groundbreaking addition to the Olympic repertoire that promises to revolutionize how we perceive athletic achievement. This blog will take you on a fascinating journey through the history, technology, and future of the Cyborg Games.
    • 11 Jun 2024
  • Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24

    SoC and IP: Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24

    GautamS
    GautamS
    PCI-SIG DevCon 2024 – 32nd Anniversary

    For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets…

    • 11 Jun 2024
  • Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification

    Analog/Custom Design: Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification

    Andre Baguenie
    Andre Baguenie
    Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera.
    • 11 Jun 2024
  • NV5 Is Optimizing Data Center Efficiency, Performance, and Reliability

    Corporate News: NV5 Is Optimizing Data Center Efficiency, Performance, and Reliability

    Tanushri Shah
    Tanushri Shah
    NV5 is a leading engineering firm at the forefront of designing AI compute data centers. They engineer, commission, and manage various projects, from underwater transmission lines to high-demand AI compute data centers. As the thermal demands of AI c...
    • 10 Jun 2024
  • Electronics Everywhere and AI-Driven Design at IMS

    Corporate News: Electronics Everywhere and AI-Driven Design at IMS

    Corporate
    Corporate
    Imagine a world where everything is electrified. From smart homes to wearable tech, we're already racing toward a future that is seamlessly digitalized thanks to cutting-edge advancements in electronics and artificial intelligence (AI). As our re...
    • 10 Jun 2024
  • Cadence CFD Advances Greener Turbomachinery at ASME Turbo Expo 2024

    Computational Fluid Dynamics: Cadence CFD Advances Greener Turbomachinery at ASME Turbo Expo 2024

    Veena Parthan
    Veena Parthan
    The ASME Turbo Expo 2024 is all about propelling towards a net-zero future in propulsion and power. This year, the focus is on evolving turbomachinery and propulsion technology for net-zero goals, highlighting disruptive technologies, sustainable ecosystems, and a collective push for innovation and sustainability.
    • 10 Jun 2024
  • Virtuoso Studio: How Do You Name Simulation Histories in Virtuoso ADE Assembler?

    Analog/Custom Design: Virtuoso Studio: How Do You Name Simulation Histories in Virtuoso ADE Assembler?

    NamrataM
    NamrataM
    This blog describes an efficient way to name the histories saved by the simulation runs in Virtuoso ADE Assembler.
    • 7 Jun 2024
  • USB4 Version 2.0 – Gen4 Link Recovery

    Verification: USB4 Version 2.0 – Gen4 Link Recovery

    Neelabh
    Neelabh

    USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.

    Here, we take an overview of the Gen4 link recovery mechanism, which is an autonomous process. It is initiated by a router when it encounters uncorrectable error events. These error events could be a timeout error…

    • 7 Jun 2024
  • Chiplet Integration in the Automotive Realm

    SoC and IP: Chiplet Integration in the Automotive Realm

    Reela Samuel
    Reela Samuel

    As technology continues to advance, the automotive industry is rapidly transforming. The integration of chiplets, or small microchips that work together to form a larger, more powerful system, is at the forefront of these advancements.

    This blog post is an excerpt from a presentation at CadenceLIVE 2024 in Silicon Valley by Pratibha Sukhija, Anunay Bajaj, and Ericles Sousa. We will examine the intricate details of chiplet…

    • 5 Jun 2024
  • Start Your Engines: Optimizing Mixed-Signal Simulation Efficiency

    Analog/Custom Design: Start Your Engines: Optimizing Mixed-Signal Simulation Efficiency

    Qingyu Lin
    Qingyu Lin
    During a mixed-signal simulation, the analog engine usually dominates the simulation time and resources. If you need to run only the analog engine in several windows, or if you would like to to run multiple tests of the same circuit with different stimuli or test pattern, then you need to run the simulation multiple times. View this blog to know more about the the two advanced technologies that Spectre AMS Designer provides…
    • 5 Jun 2024
  • The Alchemy of Wearables: Transforming Performance at the Olympics

    Corporate News: The Alchemy of Wearables: Transforming Performance at the Olympics

    Corporate
    Corporate
    The Olympic games have always been a platform for displaying the extraordinary potential of human athletes, who continually seek new ways to excel and enhance their performance. Technology enables athletes to push their limits while staying attuned ...
    • 5 Jun 2024
  • Sigrity and Systems Analysis 2024.0 Release Now Available

    System, PCB, & Package Design : Sigrity and Systems Analysis 2024.0 Release Now Available

    SigrityReleaseTeam
    SigrityReleaseTeam
    The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.0 release is now available for download at Cadence Downloads. This blog contains important links for accessing this release and introduces some of the main features that you can look forward to.
    • 5 Jun 2024
  • Accelerating Speed and Accuracy in Aeroacoustic Predictions with Fidelity LES

    Computational Fluid Dynamics: Accelerating Speed and Accuracy in Aeroacoustic Predictions with Fidelity LES

    Veena Parthan
    Veena Parthan
    Simulating aeroacoustics is a tedious task that blends the complexities of fluid dynamics with the nuances of acoustic phenomena. This blog post explores the multifaceted challenges of aeroacoustic simulations and showcases case studies where Fidelity LES has proven helpful in solving these intricate problems.
    • 4 Jun 2024
  • Virtuoso Meets Maxwell: 電磁界シミュレーションにおけるポートのふるまい

    カスタムIC/ミックスシグナル: Virtuoso Meets Maxwell: 電磁界シミュレーションにおけるポートのふるまい

    Custom IC Japan
    Custom IC Japan
    'Virtuoso Meets Maxwell'はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC-...
    • 4 Jun 2024
  • Powering Innovation: AWS Sponsors Cadence CFD F1 Student Challenge

    Corporate News: Powering Innovation: AWS Sponsors Cadence CFD F1 Student Challenge

    Corporate
    Corporate
    Partnerships are often the drivers for groundbreaking advancements in the fast-paced world of technological innovation. One such partnership that has been driving innovation forward is the collaboration between Amazon Web Services (AWS) and Cadence. ...
    • 4 Jun 2024
  • RF /マイクロ波設計: Cadence AWR の無料アカデミック トライアルで RF エンジニアリングの可能性を解き放ちましょう!

    RF Design Japan
    RF Design Japan
    RF 設計エクスペリエンスを革新する準備はできていますか?これ以上探すのはやめましょう!Cadence AWR ソフトウェアは、無線周波数 (RF) 回路設計の複雑さを習得するための入り口であり、現在、当社の独占的な無料アカデミック トライアルオファーでその実力を体験できます。 Cadence AWR を使用すると、革新と精度を両方得られる領域に足を踏み入れることができます。学生でも、経験豊富な RF エンジニアでも、無線周波数の世界への旅を始めたばかりでも、当社のソフトウェアを使用すると、比類...
    • 4 Jun 2024
  • Training Insights - The Effective Use of Filters to Narrow Down Search – Part 1

    Learning and Support: Training Insights - The Effective Use of Filters to Narrow Down Search – Part 1

    Sachin Nagpal
    Sachin Nagpal
    Today, we would like to show you how to use several filters in the Cadence Learning and Support Portal to narrow down your search and find what you are looking for quickly and easily. To access most of the links in this post, you will need a Cadence ...
    • 4 Jun 2024
  • Advancing Digital Verification with Dynamic Duo III's Accelerated Computing

    Verification: Advancing Digital Verification with Dynamic Duo III's Accelerated Computing

    Reela Samuel
    Reela Samuel

    In an era where the complexity of chip design is accelerating at an unprecedented rate, Cadence's latest innovation, the Dynamic Duo III, emerges as a beacon of advancement for chip design teams worldwide. The introduction of the Palladium Z3 Enterprise Emulation and Protium X3 Enterprise Prototyping platforms marks a significant leap forward, offering more than double the capacity and 1.5X faster performance than their…

    • 4 Jun 2024
  • Unlock Your RF Engineering Potential with a Cadence AWR Free Academic Trial!

    RF Engineering: Unlock Your RF Engineering Potential with a Cadence AWR Free Academic Trial!

    Jasmine
    Jasmine
    Are you ready to revolutionize your RF design experience? Look no further! Cadence AWR software is your gateway to mastering the intricacies of Radio Frequency (RF) circuit design, and now, you can explore its power with our exclusive Free Academic T...
    • 4 Jun 2024
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