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Unordered IO (UIO) ECN is included in the PCIe 6.1 specification and defines a new wire semantic and related capabilities for addressing the limitations of the PCI/PCIe fabric-enforced ordering rules. The key motivations for UIO ECN are to enable multiple-path fabric support and to have performance improvements.

In the PCIe protocol, there are some transaction ordering rules…

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution…

Generative AI is sweeping through every industry, re-writing the way things are done across the world. Tasks that previously required manual repetitions can now be freely automated, letting companies focus on the new rather than iterating. The field of verification is no different—and Cadence is capitalizing on this emerging technology with a wide variety of AI-powered tools that let verification engineers cut down on…

At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work.

Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources.

Adrian's excitement soared when he discovered…

The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not just reshaping how we approach design and verification in electronics; they are redefining the possibilities within the field. Our latest podcast episode delved deep into this topic, uncovering the evolutionary journey…

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition…

The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move dependency from software to hardware. 

The PCIe hierarchy can be treated as a tree that is rooted in the root port. Each hierarchy can have up to 256 buses. Each bus can host 32 devices, and each device can host eight functions…

Have you ever wondered how those tiny chips in your phone or computer actually work? It all starts with a conversation, but not in the way you might think. Here, the conversation isn't between humans but between engineers and the chips themselves. But there's a catch—they don't speak the same language!

Imagine describing a dream house—the layout, the features, the overall feel. That's similar to how…

Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal role. This approach seamlessly integrates analog and digital circuits onto a single SoC, offering notable performance, size, and power efficiency advantages.

Mixed-signal broadly refers to integrated circuits (ICs) that blend analog and digital functionalities. This designation applies not only to interfaces between these domains but…

Data management and PCB design discussions have shifted from the basics of data management to collaboration. OEMs and manufacturers shifting into system design need control of the overall design, but they can’t give up control over their IP and security. Without collaboration, there are gaps in communication and addressing problems takes longer.

How can mining your own data save time and design cycles? What are…