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The generative AI market is experiencing rapid growth, driven by the increasing parameter size of Large Language Models (LLMs). This growth is pushing the boundaries of performance requirements for training hardware within data centers. For an in-depth look at this, consider the insights provided in "HBM3E: All About Bandwidth". Once trained, these models are deployed across a diverse range of applications.…

The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems. For example, even GPT-3 at 175 billion parameters is stressing the bandwidth, capacity, training…

This blog explores how Virtuoso Studio Net Tracer can help you perform a design review.

We’ll use the net connectivity option, which allows the user to get a clean highlighted net. You can use the Net Tracer tool to highlight the nets. You can find the Net Tracer command under the connectivity pulldown menu in the layout window.

Trace manager and the ability to display different islands on the same net with other…

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges…

After the significant CHI Issue F update that introduced a number of important new features, Arm pushed forward with yet another significant update. The two salient features – Memory Encryption Contexts (MEC) and Device Assignment (DA) – further enhance the security of the Arm architecture.

Memory Encryption Contexts (MEC) is a security enhancement to the Arm Realm Management Extension introduced in CHI Issue…

In today's complex verification environments, managing debug tasks efficiently is crucial for project success. Verisium Manager, a powerful verification management tool, offers features to streamline the failure triaging process. This guide explores how to leverage these features to distribute debug tasks effectively, assign owners, and utilize built-in re-run automation for preparing waveforms in advance. 

Power saving is an important aspect in PCIe devices and to leverage this, PCIe 6.0 has introduced the L0p feature, which is a substate of the L0 LTSSM state intended to save power by disabling lanes. This feature gives the ability to change the link width without going to Recovery and Configuration LTSSM states and without stalling traffic. Complex mechanisms have been introduced into the existing design flow to accommodate…

A more appropriate title for this blog could be “All Vehicles with ADAS Need the Midas Functional Safety Platform”.

EVs tend to have advanced driving assistance systems (ADAS) because they’re newer, but not all vehicles with ADAS are EVs!

Certifying Advanced Driver Assistance Systems (ADAS) is a multifaceted process involving rigorous testing, validation, and regulatory compliance to ensure safety and…

The PCI-SIG Developers Conference 2024 is poised to be the premier event for professionals in the computing and technology sectors. Designed to unite experts and innovators worldwide, the conference features in-depth technical sessions, workshops, and demonstrations focused on advancements in PCI technology. This year's conference was in Santa Clara on June 12 and 13.

Virginia Satyro and Geeta Arora from the Cadence…

Designing 3D-ICs with integrity involves a commitment to ethical practices, reliability, and sustainability throughout the design and manufacturing process. This includes using environmentally friendly materials, ensuring robust and efficient performance, and incorporating thorough testing and verification. By prioritizing transparency, responsibility, and long-term sustainability, designers can create advanced integrated…

Near End Loopback (NELB) is a feature introduced by Intel's PHY Interface spec revision 6.1, and its general idea is to facilitate testing the PHY device for high-volume manufacturing. The loopback concept is transmitting something and receiving it back as an echo. This allows the IP to compare transmitted against received data. If there is any difference, it will be marked as an error.

The NELB happens on the pipe…