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In a persistent trend, shrinking IC geometries and higher levels of integration are leading to SoCs packed with increasingly more functionality over time. Much of this functionality is implemented in software running on systems with ever more complex architectures. This creates validation problems that go beyond RTL verification. Software functionality and performance must also be validated, prior to tape-out. Failure…

Traditionally, analog mixed signal (AMS) verification works by utilizing a connection between an RTL simulator, like Xcelium, and an analog simulator, like Spectre. Xcelium uses an R2E (real to electric) connect module to convert its input signals into an analog format that Spectre’s simulated model can understand, and then an E2R (electric to real) connect module interprets these outputs in a digital context that Xcelium…

For a while now, Cadence has led the Verification Planning and Management (VPM) domain in the EDA Industry. Cadence’s innovative and dynamic Metric-Driven Verification Methodology, or MDV, forms the backbone of the Cadence VPM tool, vManager. Now, with the latest Verisium AI platform backed by Cadence JedAI technology incorporated into its flow, Cadence’s latest Verisium Manager Tool, which was already a great tool that…

BootROM is still found in system-on-chip (SoC) designs, especially where security concerns rule out the use of booting from off-chip, non-volatile memory. While verification strategies for RTL are well-established and widely practiced, ROM verification methodologies are less well-developed and not widely standardized. Some ROM software verification approaches leverage highly integrated hardware/software co-simulation platforms…

If you missed joining or registering for the RTL-to-GDSII webinar, the complete recording is now available as a Training Byte at the Cadence support site so that you can watch and explore the complete flow, including the latest features of tools such as Xcelium Logic Simulator, Integrated Metric Center, Genus Synthesis Solution, Cadence Modus DFT Software Solution, Conformal technologies, Innovus Implementation System…

The Cadence Innovus Implementation System provides an integrated solution for RTL to GDSII design flow and is equipped to handle the most challenging designs. Each stage of the design implementation flow, such as placement, optimization, routing, and clock tree synthesis, has unique capabilities that can help the user achieve better turnaround time (TAT) and power, performance, and area (PPA). The Innovus system architecture…

Today’s high-performance electronic systems are being driven by ever-increasing complexity and density, requiring designers to consider EMI and EMC, as well as PI/SI and high-speed RF/microwave issues. To accelerate the design process and meet aggressive delivery schedules, engineers need to be able to perform EM cross-fabric and multiphysics analysis to model, simulate, and analyze these effects on chip, package, and…

The Cadence VIP portfolio is used to provide various standard protocol VIPs for testing the DUT with respective protocol interfaces. All these VIPs are released together as VIPCAT release, which is called the VIP catalog. Since these fully tested VIPs are readily available, they will play a main role in reducing the time to market for the customer DUTs.

Cadence follows consistent architecture for all its VIPs and ensures…

In the dynamic realm of system design, ensuring signals arrive unscathed at their destinations is just the tip of the iceberg. The intricacies evolve with escalating package densities, finer PCB traces, and soaring frequencies, requiring a synergy of electrical, mechanical, electromagnetic, and thermal dynamics. The growing complexities and niceties unveil the need for optimal performance, a reliable process where human…

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified.  It’s a big responsibility! Getting it right means having a good blueprint for verification closure. However, getting it wrong could result in bug escapes, wasting of resources, and possibly leading to a device failing altogether. In fact, verification planning…

Power integrity is becoming one of the most pressing challenges at advanced nodes, with designers regularly facing a significant number of EMIR violations at signoff.

In this era of pervasive data, hyper-connectivity, and artificial intelligence, design size is constantly increasing, and the popularity of 3D-IC design is adding another dimension to power integrity complexity.

To overcome those challenges, it is imperative…

Maintaining connectivity during custom layout creation enables key capabilities of Cadence’s custom layout flow. This helps you accurately predict and optimize the performance of your circuits—significantly boosting your layout productivity.

Virtuoso Studio’s custom design solution has new features that let you preserve the connectivity of virtually all custom designs.

Join Cadence Training and Sr…