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Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics of ATS request-completion…

Companies are under extreme pressure to get new products to market faster, ahead of the competition and without issues. To do so, design teams need to shorten their design and manufacturing cycles. But how do you achieve that?

What would happen if you changed from the traditional design methodology of ECAD and MCAD groups working independently and then hoping the final product can be assembled without issues? What options…

Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Maybe you've been curious about the role of rule deck writers in creating high-quality designs ready for tape-out.

If any of these questions interest you, there is good news: the latest…

PCIe technology has evolved over three decades, marking its 30th anniversary with the unveiling of PCIe 7.0. This latest standard doubles IO bandwidth to 128GT/s, emphasizing low latency and high reliability while maintaining compatibility with previous generations. Key features on the physical layer include the adoption of PAM4 signaling, 1b/1b encoding, and a robust Forward Error Correction…

Unordered IO (UIO) ECN is included in the PCIe 6.1 specification and defines a new wire semantic and related capabilities for addressing the limitations of the PCI/PCIe fabric-enforced ordering rules. The key motivations for UIO ECN are to enable multiple-path fabric support and to have performance improvements.

In the PCIe protocol, there are some transaction ordering rules…

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution…

Generative AI is sweeping through every industry, re-writing the way things are done across the world. Tasks that previously required manual repetitions can now be freely automated, letting companies focus on the new rather than iterating. The field of verification is no different—and Cadence is capitalizing on this emerging technology with a wide variety of AI-powered tools that let verification engineers cut down on…

At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work.

Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources.

Adrian's excitement soared when he discovered…