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The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not just reshaping how we approach design and verification in electronics; they are redefining the possibilities within the field. Our latest podcast episode delved deep into this topic, uncovering the evolutionary journey…

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition…

The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move dependency from software to hardware. 

The PCIe hierarchy can be treated as a tree that is rooted in the root port. Each hierarchy can have up to 256 buses. Each bus can host 32 devices, and each device can host eight functions…

Have you ever wondered how those tiny chips in your phone or computer actually work? It all starts with a conversation, but not in the way you might think. Here, the conversation isn't between humans but between engineers and the chips themselves. But there's a catch—they don't speak the same language!

Imagine describing a dream house—the layout, the features, the overall feel. That's similar to how…

Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal role. This approach seamlessly integrates analog and digital circuits onto a single SoC, offering notable performance, size, and power efficiency advantages.

Mixed-signal broadly refers to integrated circuits (ICs) that blend analog and digital functionalities. This designation applies not only to interfaces between these domains but…

Data management and PCB design discussions have shifted from the basics of data management to collaboration. OEMs and manufacturers shifting into system design need control of the overall design, but they can’t give up control over their IP and security. Without collaboration, there are gaps in communication and addressing problems takes longer.

How can mining your own data save time and design cycles? What are…

New additions, including first-to-market VIP for PCIe 7.0, Ethernet 1600G, GDDR7, next-gen HBM, and DFI next-gen HBM, enable fast and comprehensive verification, ensuring SoCs meet specifications for the latest standards protocols

Cadence recently announced the extension of its Verification IP (VIP) portfolio to include support for new VIP for emerging high-speed interfaces critical in data-intensive domains, such as…

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low…