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PCB、IC封装：设计与仿真分析: IC封装中快速创建结构的新方法

TeamAllegro

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年，专注于IC封装与中介层基板设计。同时，参与全Allegro平台、Virtuoso、PVS、OrbitIO及 Innovus产品的核心工作。 space Allegro® Package Designer Plus工具在最新的17.4版本中迎来了布线技术中的新变化——广为人知的...
- 24 Jun 2022
Breakfast Bytes: I Came to the US 40 Years Ago Today

Paul McLellan

Today, I'm going to be a bit self-indulgent. It is the 40th anniversary of when I emigrated from the United Kingdom to the US. I think it was only the third time I'd been to the US. I'd visited in 1979 for a conference and also visited Ca...
- 24 Jun 2022
カスタムIC／ミックスシグナル: Virtuosity: 信頼性解析レポート－信頼性解析の結果をインタラクティブに

Custom IC Japan

私たちは、製品を使いやすく、簡単にアクセスできるようにし、視覚的にも魅力的なものにすることがユーザビリティのアイデアであると考えています。私たちは、製品のユーザビリティを向上させるために常に努力しています。産業、医療、航空宇宙、自動車などのミッションクリティカルな用途におけるICの利用増加により、確実な信頼性の解析の必要性が、最も重要な項目になりました。デバイス特性の低下、モデルパラメータの変化、自己発熱の影響などの劣化の影響の測定と評価を行うために、長年に渡ってVirtuoso ADE...
- 23 Jun 2022
Breakfast Bytes: embedded world 2022

Paul McLellan

Every year, in early March, Embedded World takes place (or embedded world, as they like to call it, all in lower-case). It is always in Nuremberg, a couple of hours north of Munich. It was completely virtual the last couple of years, and it was postp...
- 23 Jun 2022
PCB、IC封装：设计与仿真分析: 利用 HEMT 和 PHEMT 改善无线通信电路中的增益、速度和噪声

SDA China

本文要点高电子迁移率晶体管 (High electron mobility transistors ，HEMT) 和伪高电子迁移率晶体管 (pseudomorphic high electron mobility transistors ，PHEMT) 因其独特的、可提高性能的特点而大受欢迎在 HEMT 结构中，高电子迁移率是由于掺杂的宽带半导体与未掺杂的窄带隙半导体并列在一起造成的 HEMT 和 PHEMT 常见于移动电话、卫星电视接收器、雷达和低噪声放大器用于无线通信放大器和转换器...
- 22 Jun 2022
Breakfast Bytes: CadenceLIVE: Intel Foundry Services

Paul McLellan

One of the potentially significant events in the foundry marketplace is the creation of Intel Foundry Services (IFS). This was announced by CEO Pat Gelsinger after about a month in the new job, and I wrote about it in my post, The New Intel Foun...
- 22 Jun 2022
Verification: 5X “Time Warp” in Your Next Verification Cycle Using Xcelium Machine Learning

Anika Sunda

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...
- 21 Jun 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution

kgjudd

I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into Virtuoso RF Solution?" I am excited about new functionality in the latest ICADVM20.1 ISR25 release. It is a new GUI under the Tools menu called Enablement.
- 21 Jun 2022
Breakfast Bytes: W. Edwards Deming: A Prophet Ignored in His Own Land

Paul McLellan

Thirty years ago last Friday, 17th June 1992, I went to Seattle to attend a two-day seminar by W. Edwards Deming. At the time I was the VP of Engineering at Compass Design Automation, meaning I was in charge of all product development. I just looked...
- 21 Jun 2022
Computational Fluid Dynamics: Women in CFD with Carolyn Woeber

Veena Parthan

Few words from Carolyn Woeber, applications engineering director at Cadence, about her experience working her way through different roles and projects to stand where she is today.
- 20 Jun 2022
PCB、IC封装：设计与仿真分析: Omnis Marine 如何通过优化船舶纵倾，节省高达 5%的燃料？

SDA China

本文作者：Maurits Van Den Boogaard, Cadence CFD Product Engineer space 在谈到航运业节能减排时，大家可能不会想到从纵倾优化的角度入手；但这种方法在近期备受关注，因为它确实可以大大减少燃料消耗。即使航行速度和吃水保持不变，船舶的阻力也会发生变化，这取决于纵倾角度。因此，在港口的装载货物时，优化纵倾角可以确保船舶在航行过程中的平均阻力达到最小。纵倾优化的经济效益除了助力环保事业，航运公司还可以获得梦寐以求的经济效益。由于优化纵倾角可以减...
- 20 Jun 2022
PCB、IC封装：设计与仿真分析: 2022 PCB网课 | Allegro PCB进阶设计系列课程

TeamAllegro

成为资深PCB工程师必备的能力，是面对复杂设计时，从容地做好前期规划（规则框架、布局规划、布线规划），并凭借对于工具的熟悉度，有效落实这些规划。如此，才能在追求PCB板体积更小、密度更大、交付时间更紧迫的行业现况中脱颖而出。 “Allegro PCB进阶设计” 系列课程的设计，旨在帮助希望成长为资深工程师的学员们，通过设计实例系统学习、高效达标。让我们一起来弯道超车吧！识别下图二维码，免费报名参加直播或观看录播回放： space 欢迎订阅“PCB、IC封...
- 16 Jun 2022
Breakfast Bytes: Offtopic: The Mini

Paul McLellan

Today is the last day before a break so I'm going off topic as usual. Tomorrow is a Cadence Global Recharge Day (all of Cadence is shut down) and Monday is Juneteenth (a U.S. federal holiday as of last year). If you watch the Sunday Brunch videos I m...
- 16 Jun 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre Xシミュレーションのパフォーマンスを向上させる方法

Custom IC Japan

シミュレーションのパフォーマンスは、チップの設計、検証、およびサインオフに必要な時間の重要な要素の一つです。シミュレーションが効率的であるほど、テープアウトに必要なリソースと所要時間は少なくなります。シミュレーションパフォーマンスを最適化する方法について設計者の意識を高めることで、設計チームの生産性が大幅に向上し、ライセンスの使用量やコンピューティング・ファームの要件に至るまで、設計全体のリソースを効率的に使用できるようになります。設計段階と検証段階では、シミュレーションの精度とパフォーマンス...
- 15 Jun 2022
Breakfast Bytes: HOT CHIPS 34 Preview

Paul McLellan

Every Summer, one of the most interesting conferences I attend is HOT CHIPS. Often the presentations themselves are interesting since they describe some of the highest-performance chips that are either recently shipping or soon to be shipping. But a...
- 15 Jun 2022
PCB、IC封装：设计与仿真分析: 汽车行业新标准：ISO 21434

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Have You Heard of ISO 21434? You Will”。 space 相信不少人都已熟知汽车行业的ISO 26262标准，这是一项有关汽车电气和（或）电子（E/E）系统功能安全的国际标准。如需了解详细信息，请参阅：汽车行业合规与功能安全指南：ISO2626 标准出台十周年 ISO 21434 ISO 26262...
- 14 Jun 2022
Breakfast Bytes: CadenceLIVE Silicon Valley 2022

Paul McLellan

CadenceLIVE Silicon Valley took place last week. It turned out to be the second in-person event that I attended that week since I was also at the first couple of days of the RSA Conference up in San Francisco. It was good to escape from sitting in fr...
- 14 Jun 2022
Verification: Quest for Bugs – The Constrained-Random Predicament

Anika Sunda

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.
- 14 Jun 2022
Breakfast Bytes: RSAC 2022: The Cryptographer's Panel

Paul McLellan

The biggest security conference in the world is RSAC, held in San Francisco. It fills all three buildings of the Moscone Center. Some of the monitors around display some interesting statistics, such as the over 400 exhibitors shipped over 225 tons to...
- 13 Jun 2022
Computational Fluid Dynamics: Insights on Automotive Industry with Kumar

Veena Parthan

Get insights into the changes happening in the automotive industry and the role of simulation in system design integration and optimization with Kumar Srinivasan, Sr. Technical Director responsible for CFD Solutions at Cadence.
- 12 Jun 2022
Breakfast Bytes: Optimal Design of High-Speed Flexible Interconnectors Using Deep Learning

Paul McLellan

At the recent DesignCon 2022, Kyle Chen of Microsoft and Suomin Cui of Cadence jointly presented Optimal Design of High-Speed Flexible Interconnectors by Applying DL Optimization and 3D Electromagnetic Solvers. Kyle is an SI/PI engineer for mixed rea...
- 10 Jun 2022
Breakfast Bytes: Optimality Intelligent System Explorer

Paul McLellan

As a kid, I remember reading something that passed for a joke: We are leaving the push-button age, and entering the age where the buttons push themselves. If you look at developments in advanced driver assistance systems (ADAS) and autonomous driv...
- 9 Jun 2022
Analog/Custom Design: Virtuosity: Reliability Analysis Report-Reliable Results Made Interactive

Udit Rajput

Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.
- 9 Jun 2022
Breakfast Bytes: Cadence OnCloud SaaS and e-Commerce Platform, the Next Step of Cadence's Cloud Journey

Paul McLellan

Today at CadenceLIVE Silicon Valley, Anirudh Devgan, Cadence's CEO, announced the OnCloud SaaS and e-Commerce Platform (or Cadence OnCloud to its friends) during his keynote. I recently wrote about the long history of Cadence Cloud in my po...
- 8 Jun 2022
PCB設計／ICパッケージ設計: ASCENT: 進化するライブラリに合わせてデザインを管理する

SPB Japan

パーツは PCB デザインの基本的な要素です。デザインに含まれるパーツとそのグラフィック、電気的特性、パーツ定義情報を、アップデートされていく最新ライブラリの内容に合わせることは大変重要です。回路図ライブラリは、最新の技術進歩や安全規格の改版に加え、企業固有のパーツ属性、例えばリードタイムやコスト、ライフサイクルなどに基づいて継続的に更新されます。定期的あるいはより急速に進化するライブラリと連動し、設計進行中のデザインに対して最新のパーツ情報による更新を正確かつ自動的に行う必要があります。 &n...
- 8 Jun 2022

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