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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? The Secret's in the 16.5 Release!

The Allegro Design Workbench (ADW) Configuration Manager application is designed…

• 1 min read
PCB , data management , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , design data management , configuration manager , design , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Event Report: Club Formal Shanghai

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and…

• 2 min read
events , Verification IP , China , ABV , verification strategy , Functional Verification , ABVIP , formal , ADS , assertions , Club Formal , IEV , Assertion-Driven Simulation , Shanghai , Formal verification , IFV , Jin Tang , Assertion-based verification

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 4

In several previous postings we introduced the problem of solving the sudoku puzzle…

• 6 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Verification

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots…

Recently I had the honor of presenting the functional verification roadmap at CDNLive…

• 2 min read
Suman Ray , Low Power , Joe Hupcey III , ABV , Apurva Kalia , verification strategy , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Manu Chopra , Incisive , Lokesh Pundreeka , SVA , Lego , assertions , robot , MDV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About Refresh, Copy Project, TCL in SCM? 16.5 Has a Few New Enhancements

There are several enhancements in the 16.5 System Connectivity Manager ( SCM ) /…

• less than a min read
PCB , SCM , Allegro Design Entry , Constraint-driven PCB Design flow , refresh option , Allegro 16.5 , ASA , Allegro System Architect (ASA) , Front-end PCB design , Design Entry , SPB16.5 , copy project , Schematic , Allegro , tcl

Verification

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

Please join Team Verify and other D&V engineers for one or both of the following…

• 1 min read
scoreboard , ABV , methodology , verification strategy , Joerg Mueller , Functional Verification , Formal Analysis , formal , EDA360 , webinar , Club Formal , IEV , Formal verification , IFV , Assertion-based verification

Digital Design

CDNLive! Silicon Valley 2012 Abstracts Due November 11th, 2011

The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November…

• 1 min read
CDNLive , cadence , encounter , Cadence users , Digital Implementation , CDNLive!

Analog/Custom Design

Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an…

• 1 min read
real value , Verilog-AMS , analog , Mixed-Signal , analog behavoral , Verilog , Virtuoso , Fred , mixed signal , wreal , SPICE

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 2

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

• 3 min read
RF , RF Simulation , analog/RF , HB , Spectre RF , ADE-L , MMSIM , Virtuoso Spectre Simulator GXL , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance

System, PCB, & Package Design 

What's Good About Single Mode Operation in DEHDL? The Secret's in the 16.5 Release

Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require…

• 12 min read
PCB , Allegro Design Entry , DEHDL , Allegro 16.5 , Design Entry HDL , Front-end PCB design , design , PCB design , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro , single mode operation

Analog/Custom Design

How Fred Discovered Mixed-Signal Behavioral Modeling

Introduction This is the first of a series of blogs where we will add pieces to the…

• 3 min read
AMS , mixed signal design , AMS-Designer , Verilog-AMS , analog , Mixed-Signal , Virtuoso , Fred , assertions , mixed signal , wreal

Analog/Custom Design

A Moment to Mourn -- John McCarthy, Father of Lisp

Here lies a Lisper Uninterned from this mortal package Yet not gc'd While we…

• 1 min read
John McCarthy , McCarthy , software development , Lisp , Custom IC Design , SKILL

Verification

Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for…

• 4 min read
zynq , virtual platforms , TLM , EPP , Zynq-7000' , virtual prototypes , Cortex-A9 , System Design and Verification , software , SystemC , xilinx , ARM , linux , extensible , FPGA

Verification

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

• 2 min read
NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Verification

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

• 3 min read
ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

System, PCB, & Package Design 

What's Good About PCB SI IOCell Editor in Model Editor? 16.5 Has a Few New Enhancements

There are currently multiple options for model editing in the Allegro PCB SI environment…

• 2 min read
PCB SI , PCB , SI , I/O , SiP , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , High Speed , Allegro 16.5 , SigWave , Signal Integrity , Allegro PCB SI , PCB design , SPB16.5 , IOCell Editor , SI analysis and modeling , model editor , library , Allegro

Verification

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual…

• 4 min read
Virtual System Platform , virtual platforms , Quantum Platform , virtual prototypes , dining philosophers , UART , System Design and Verification , RTOS tracing , QP , software , qspy

Verification

Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming…

• 1 min read
SystemVerilog , uvm , OVM ML , Functional Verification , webinar , multi-language , SystemC , IES

System, PCB, & Package Design 

What's Good About APD’s Die Abstract Compare? You’ll Need the 16.5 Release to See

In the distributed co-design environment in the SPB16.5 Allegro Package Designer…

• 4 min read
PCB , SiP , IC Packaging , packaging , SiP Design , APD , Allegro 16.5 , IC/package co-design , PCB Editor , Allegro Package Designer , Layout , design , PCB design , die abstract compare , SPB16.5 , die abstract , Allegro
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