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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 18-20 is the annual…

• 3 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

SoC and IP

Cross Currents in Memory Market Signal Changes Ahead

No one can say with any certainty, but... Recent improvements in DRAM and NAND…

• 6 min read

Verification

Modeling Interfaces with C-to-Silicon Compiler

Users of ESL tools are curious about the procedure for handling the interface to…

• 2 min read
CTOS , System Design and Verification , TLM 2.0 , SystemC analysis , C-to-Silicon , transaction level modeling , high level synthesis , Modeling , HLS , dma

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 3

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM…

• 7 min read
TLM , simvision , System Design & Verification , ESL

Verification

e Coding Made Easy with the “DVT” Integrated Development Environment

Specmaniacs everywhere should be aware of a great, full-featured integrated development…

• 6 min read
IEEE 1647 , SystemVerilog , eclipse , Specman , CDNLive , Functional Verification , OVM , OVM e , OVM SV , e , specman elite , AMIQ , eRM

Verification

It's Not Too Early to Think About DAC 2009

Even though it's still a couple of months off, it's not too early to think about…

• 1 min read
DAC 2009 , System Design and Verification , hardware-dependent software

Verification

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Analog/Custom Design

Jurassic Park IV: The Return of ANALOG

In the lab, no one can hear you scream! When I was getting my BSEE in the…

• 2 min read
analog , Incisive , encounter , Virtuoso , RF design , Custom IC Design

Digital Design

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Digital Design

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Analog/Custom Design

An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso…

The emergence of sub-micron technologies has enabled today’s designers to include…

• 1 min read
CDNLive , Virtuoso , Spectre , RF design , MDL

Verification

Using Macros for Repetitive Coding Tasks

For this post welcome guest blogger Hilmar van der Kooij. Hilmar is a Cadence Application…

• 5 min read
Specman , Functional Verification , tech tips , OVM , OVM e , Coverage-Driven Verification , team specman , Aspect Oriented Programming , macros , AOP

SoC and IP

Early Returns on 1Q09 Financials

Memory Companies Suffer More in 1Q09, but Future Looks Better...or so they say: …

• 4 min read

RF Engineering

Enhanced pnoise Algorithm to Compute Phase-Noise for VCOs with Bandgap Voltage R…

Accurate phase-noise characterization is critical in the design of RF and microwave…

• 1 min read
DC , MMSIM , IC Voltage , RF design , VCO

Verification

Some SystemC Perspectives - An Interview with Vincent Motel

I sat down with Vincent Motel recently, a long time Cadence employee, and one of…

• 7 min read
OVM , C-to-Silicon , System Design & Verification , SystemC: OCSI

System, PCB, & Package Design 

What's Good About Relational Table Support in Capture-CIS? You'll Need SPB16.2 to

With SPB16.2 release, Capture-CIS allows you to create and use relational tables…

• 2 min read
SPB 16.2 , Functional Verification , Capture-CIS , RDBMS , Allegro

Analog/Custom Design

Getting a Feel for RF

It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine…

• 2 min read
MMSIM , Virtuoso Analog Design Environment , Virtuoso , RF design , Circuit Design , Simulators , Custom IC Design

SoC and IP

Industry Downturn Perspectives..Forward and Backward

Recent Results Signal Better Times Ahead; How Much Better?...Little Consensus,…

• 9 min read

Verification

Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share…

• 2 min read
IEEE 1647 , performance , events , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , temporal expressions , OVM-e , specman elite , IES , IES-XL
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