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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

SoC and IP

HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF

High-performance and high-speed memory design characterized by low-power operation…

• 2 min read
DDR4 , electronic system design , cadence , IP blocks , TSMC , 16nm , FinFET , Hisilicon

SoC and IP

Cadence at CES 2015: Enabling Surreal Surround Sound Audio

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine…

• 1 min read
DTS , Consumer Electronics , cadence , surround sound , audio , Tensilica , HiFi DSP , CES 2015 , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Voltage and Monitoring IP

In this week's Whiteboard Wednesdays, Bob Salem discusses voltage and monitoring…

• less than a min read
IP , voltage and monitoring IP , temperature tracking , intellectual property

SoC and IP

Cadence Firmware Packages Enable Successful IP Integration

Building a system on chip (SoC) from IP blocks requires system-level integration…

• 3 min read
Bring-up , IP integration , ip cores , firmware

SoC and IP

Get a Glimpse at New Ethernet Standards in the Works

I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet…

• 2 min read
25G Ethernet , new Ethernet standards , Ethernet standards , Automotive Ethernet , IEEE 802.3 , ip cores , Ethernet

Verification

Dealing with the "Throw it Over the Wall" Methodology in Power Supply Network De…

"Throw it over the wall" is business slang for completing your part of a project…

• 2 min read
PSN , Power Supply Network , debug , Functional Verification , power-aware , UPF

Verification

Searching Through a Complex Design? DFS to the Rescue!

Recently, while at a customer site, I was faced with the huge task of looking for…

• 4 min read
Functional Verification , simvision , design file search , Incisive Enterprise Simulator (IES)

Whiteboard Wednesdays

Whiteboard Wednesdays—Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applica…

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey…

• less than a min read
Whiteboard Wednesdays , IP , LPDDR4 , 32-bit

SoC and IP

Cadence at CES 2015: Power-Sensitive Always-On Systems

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user…

• less than a min read
audio , power management , HiFi Mini , Tensilica , Realtek Semiconductor , HiFi DSP , CES 2015

Verification

Lazy Test Cases for Tool Failures Using the Testcase Optimizer (TCO)

The Current State It seems to be a fact of life that software has bugs and, unfortunately…

• 7 min read
performance , methodology , verification strategy , debug , tech tips , Incisive , universal verification methodology , verification

SoC and IP

Cadence at CES 2015: A Look at Face-Detection Technology

LAS VEGAS—A key function of automotive, IoT, security, and similar applications is…

• less than a min read
IP , cadence , IVP , Xtensa , CES 2015 , image processing , video processing

Whiteboard Wednesdays

Whiteboard Wednesdays—New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey…

• less than a min read
Whiteboard Wednesdays , LPDDR4 , DBI , LVSTL

SoC and IP

Cadence at CES 2015: The IP Story

LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just…

• less than a min read
ip cores semiconductor IP , EDA companies , Martin Lund , IP design , CES 2015

SoC and IP

My Top 10 List from CES

After nearly a week at CES, almost everyone is asking me – what was the big thing…

• 4 min read
DSP , Design IP , IP , CES , audio , video , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things , imaging

System, PCB, & Package Design 

Customer Support Recommended—Modeling Voltage-Controlled Oscillators (VCO) Using…

A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation…

• 2 min read
AMS , Allegro 16.6 , Allegro 16.5 , PSPICE , PCB design , SPB16.5

Whiteboard Wednesdays

Whiteboard Wednesdays—Soundwire Audio Interface

In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles…

• less than a min read
Whiteboard Wednesdays , IP , audio , MIPI , Soundwire

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Customization Capabilities? 16.6 has Several New…

The 16.6 release of OrCAD Capture/Capture-CIS provides several areas for you to customize…

• 2 min read
OrCAD Capture , 16.6 , Capture CIS , Grzenia , Schematic

Verification

Using Generative List Pseudo Methods in Constraints – A Case Study

This article highlights the use of list pseudo-methods constraining the content of…

• 2 min read
Specman , list pseudo-methods , Ethernet , constraint coding , debugging

SoC and IP

Cadence at CES 2015: Experience Integrated Solutions for Mobile

Given that CES is a novelty-focused event, it is crucial that innovative companies…

• 2 min read
Design IP , cadence , Consumer Electronics Show , CES , DIP , DSI , Tensilica , CES 2015 , MIPI D-PHY
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